Pattern mapping method for low power bist based on transition freezing method

Youbean Kim, Jaewon Jang, Hyunwook Son, Sungho Kang

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

Proposed in this paper is a low power BIST architecture using the pattern mapping method based on the transition freezing method. The transition freezing method generates frozen patterns dynamically according to the transition tendency of an LFSR. This leads to an average power reduction of 60%. However, the patterns have limitations of 100% fault coverage due to random resistant faults. Therefore, in this paper, those faults are detected by mapping useless patterns among frozen patterns to the patterns generated by an ATPG. Throughout the scheme, 100% fault coverage is achieved. Moreover, we have reduced the amount of applied patterns, the test time, and the power dissipation.

Original languageEnglish
Pages (from-to)643-646
Number of pages4
JournalIEICE Transactions on Information and Systems
VolumeE93-D
Issue number3
DOIs
Publication statusPublished - 2010 Jan 1

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Freezing
Built-in self test
Energy dissipation

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering
  • Artificial Intelligence

Cite this

Kim, Youbean ; Jang, Jaewon ; Son, Hyunwook ; Kang, Sungho. / Pattern mapping method for low power bist based on transition freezing method. In: IEICE Transactions on Information and Systems. 2010 ; Vol. E93-D, No. 3. pp. 643-646.
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Pattern mapping method for low power bist based on transition freezing method. / Kim, Youbean; Jang, Jaewon; Son, Hyunwook; Kang, Sungho.

In: IEICE Transactions on Information and Systems, Vol. E93-D, No. 3, 01.01.2010, p. 643-646.

Research output: Contribution to journalArticle

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