Abstract
The increasing speed of advanced chip technologies has greatly challenged the interconnection methods and processes in order to achieve enhanced capability. We have successfully fabricated the solder bump and it's reflowing process for flip-chip bonding interconnection technique instead of conventional wire bonding for high speed devices. The lead(Pb: 350°C) and the Indium(In: 157°C) were used for solder bump and deposited by using thermal evaporation. The thickness of the deposited metal for solder bump was in the range of 5approx.6μm thickness. Specially, to increase the accuracy and the reliability of the flip-chip bonding Technique, 3 layer thick photoresist about 30μm was used to control the deposition area for solder bump. It was also used for the lift-off process of excess deposited metal for solder bump. The height of solder bump through the reflowing process was controlled in the range of 10approx.40μm according to the deposited area and shape. Also, the deposited area and shape was one of the most important parameters for solder bump fabrication. In addition, it was found that an oxidized surface layer effects on the increased melting temperature of deposited metal for solder bump. In this process, the reflowing temperature of PB/In (60:40 wt%) solder bumps was 230±5°C.
| Original language | English |
|---|---|
| Pages | 421-424 |
| Number of pages | 4 |
| Publication status | Published - 1996 Dec 1 |
| Event | Proceedings of the 1996 IEEE Asia Pacific Conference on Circuits and Systems - Seoul, South Korea Duration: 1996 Nov 18 → 1996 Nov 21 |
Other
| Other | Proceedings of the 1996 IEEE Asia Pacific Conference on Circuits and Systems |
|---|---|
| City | Seoul, South Korea |
| Period | 96/11/18 → 96/11/21 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
Cite this
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Pb/In solder bump formation for a flip-chip bonding technique at high speed optical communication devices. / Han, Haksoo; Chung, Hyunsoo; Park, Sungkook; Joe, Yungil; Park, Sungsoo; Joo, Gwanchong; Hwang, Nam; Lee, Hee Tae; Seungoo, Kang; Min-Kyu, Song.
1996. 421-424 Paper presented at Proceedings of the 1996 IEEE Asia Pacific Conference on Circuits and Systems, Seoul, South Korea, .Research output: Contribution to conference › Paper
TY - CONF
T1 - Pb/In solder bump formation for a flip-chip bonding technique at high speed optical communication devices
AU - Han, Haksoo
AU - Chung, Hyunsoo
AU - Park, Sungkook
AU - Joe, Yungil
AU - Park, Sungsoo
AU - Joo, Gwanchong
AU - Hwang, Nam
AU - Lee, Hee Tae
AU - Seungoo, Kang
AU - Min-Kyu, Song
PY - 1996/12/1
Y1 - 1996/12/1
N2 - The increasing speed of advanced chip technologies has greatly challenged the interconnection methods and processes in order to achieve enhanced capability. We have successfully fabricated the solder bump and it's reflowing process for flip-chip bonding interconnection technique instead of conventional wire bonding for high speed devices. The lead(Pb: 350°C) and the Indium(In: 157°C) were used for solder bump and deposited by using thermal evaporation. The thickness of the deposited metal for solder bump was in the range of 5approx.6μm thickness. Specially, to increase the accuracy and the reliability of the flip-chip bonding Technique, 3 layer thick photoresist about 30μm was used to control the deposition area for solder bump. It was also used for the lift-off process of excess deposited metal for solder bump. The height of solder bump through the reflowing process was controlled in the range of 10approx.40μm according to the deposited area and shape. Also, the deposited area and shape was one of the most important parameters for solder bump fabrication. In addition, it was found that an oxidized surface layer effects on the increased melting temperature of deposited metal for solder bump. In this process, the reflowing temperature of PB/In (60:40 wt%) solder bumps was 230±5°C.
AB - The increasing speed of advanced chip technologies has greatly challenged the interconnection methods and processes in order to achieve enhanced capability. We have successfully fabricated the solder bump and it's reflowing process for flip-chip bonding interconnection technique instead of conventional wire bonding for high speed devices. The lead(Pb: 350°C) and the Indium(In: 157°C) were used for solder bump and deposited by using thermal evaporation. The thickness of the deposited metal for solder bump was in the range of 5approx.6μm thickness. Specially, to increase the accuracy and the reliability of the flip-chip bonding Technique, 3 layer thick photoresist about 30μm was used to control the deposition area for solder bump. It was also used for the lift-off process of excess deposited metal for solder bump. The height of solder bump through the reflowing process was controlled in the range of 10approx.40μm according to the deposited area and shape. Also, the deposited area and shape was one of the most important parameters for solder bump fabrication. In addition, it was found that an oxidized surface layer effects on the increased melting temperature of deposited metal for solder bump. In this process, the reflowing temperature of PB/In (60:40 wt%) solder bumps was 230±5°C.
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M3 - Paper
AN - SCOPUS:0030392935
SP - 421
EP - 424
ER -