3D NAND flash memories promise unprecedented flash storage capacities, which can be extremely important in certain application domains where both storage capacity and performance are first-class target metrics. However a block of 3D NAND flash contains many more pages than its 2D counterpart. This increased number of pages-per-block has numerous ramifications such as the longer erase latency, higher garbage collection costs, and increased write amplification factors, which can collectively prevent the 3D NAND flash products from becoming the mainstream in high-performance storage domain. In this paper, we introduce PEN, an architecture-level mechanism that enables partial-erase of flash blocks. Using our proposed partial-erase support, we also discuss how one can build a custom garbage collector for two types of flash translation layers (FTLs), namely, block-level FTL and hybrid FTL. Our experimental evaluations of PEN with a set of diverse real storage workloads indicate that the proposed approach can shorten the write latency by 44.3% and 47.9% for block-level FTL and hybrid FTL, respectively.
|Title of host publication||Proceedings of the 16th USENIX Conference on File and Storage Technologies, FAST 2018|
|Number of pages||16|
|Publication status||Published - 2018|
|Event||16th USENIX Conference on File and Storage Technologies, FAST 2018 - Oakland, United States|
Duration: 2018 Feb 12 → 2018 Feb 15
|Name||Proceedings of the 16th USENIX Conference on File and Storage Technologies, FAST 2018|
|Conference||16th USENIX Conference on File and Storage Technologies, FAST 2018|
|Period||18/2/12 → 18/2/15|
Bibliographical noteFunding Information:
This research is supported by NSF grants 1439021, 1439057, 1409095, 1626251, 1629915, 1629129 and 1526750, and a grant from Intel. Dr. Jung is supported in part by NRF 2016R1C1B2015312, DOE DE-AC02-05CH 11231, IITP-2017-2017-0-01015, NRF-2015M3C4A7065645, and MemRay grant (2015-11-1731). Kandemir and Jung are the co-corresponding authors. The authors thank Prof. Youjip Won for shepherding this paper.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Computer Networks and Communications