Pentacene thin-film transistors with polymer TiOx double-layer dielectrics operating at 3 v

Kyunghee Choi, D. K. Hwang, Kimoon Lee, Jae Hoon Kim, Seongil Im

Research output: Contribution to journalArticle

13 Citations (Scopus)

Abstract

We report on the fabrication of low-voltage pentacene thin-film transistors (TFTs) adopting poly-4-vinylphenol (PVP)/titanium oxide (TiOx) double-layer dielectrics deposited on an indium-tin oxide glass substrate. The total capacitance of the 45 nm thick PVP100 nm thick (or 200 nm thick) TiOx double-layer dielectric was as high as 57-61 nF cm2 while the k values turn out to be 25-34. Despite small dielectric strength (∼0.6 MVcm) of high- k TiOx layers, our pentacene TFT with the 45 nm thick PVP100 nm thick TiOx double-layer dielectric exhibited an excellent mobility and an on/off current ratio of 1.52 cm2 V s and ∼1× 103, respectively, operating at a low gate voltage of -3 V.

Original languageEnglish
Pages (from-to)H114-H116
JournalElectrochemical and Solid-State Letters
Volume10
Issue number3
DOIs
Publication statusPublished - 2007

All Science Journal Classification (ASJC) codes

  • Chemical Engineering(all)
  • Materials Science(all)
  • Physical and Theoretical Chemistry
  • Electrochemistry
  • Electrical and Electronic Engineering

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