Performance Optimization and Improvement of Silicon Avalanche Photodetectors in Standard CMOS Technology

Myung Jae Lee, Woo Young Choi

Research output: Contribution to journalArticle

8 Citations (Scopus)

Abstract

This paper discusses design optimization for silicon avalanche photodetectors (APDs) fabricated in standard complementary metal-oxide-semiconductor (CMOS) technology in order to achieve the highest possible performance. Such factors as PN junctions, guard ring structures, active areas, and back-end structures are considered for the optimization. CMOS-APDs reflecting varying aspects of these factors are fabricated and their performances are characterized. In addition, their characteristics are analyzed with technology computer-aided-design simulations and equivalent circuit models. From these investigations, dominant factors that influence the CMOS-APD performance are identified. Furthermore, three different techniques enabling further performance improvements of CMOS-APDs are investigated, which are spatial-modulation, carrier-acceleration, and multijunction techniques. The state-of-the-art CMOS-APDs' structures and performances are presented and compared, and the best optimized CMOS-APD is proposed. These results should be extremely useful for realizing optimal silicon APDs in standard CMOS technology for various applications.

Original languageEnglish
Article number8047267
JournalIEEE Journal of Selected Topics in Quantum Electronics
Volume24
Issue number2
DOIs
Publication statusPublished - 2018 Mar 1

All Science Journal Classification (ASJC) codes

  • Atomic and Molecular Physics, and Optics
  • Electrical and Electronic Engineering

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