Performance simulations and verification for power/ground planes connected with ground area-fills on multi-layer PCBs

This paper deals with the effect of ground area-fill which affects the impedance of power distribution network (PDN) in the general desktop-PC motherboard. The outer area-fills connected to inner power/ground planes are modeled in equivalent cell-mesh structure. The unit cell is composed of circuit elements, encompassing the effect of DC and frequency dependent loss. Vector network analyzer (VNA) is employed for measurement and excellent agreement between the proposed model and simulated result has been obtained. Furthermore, the performance simulation for various arrangements of vias and area-fill is performed based on modeling method presented before. The vias connected with area-fill assess the impedance behavior of power/ground planes. According to the widely known strategy of placement of decoupling capacitor, several simulations are performed. All distributed vias at the area-fill have the same results of distributing all vias at the edge of area-fill at the view of impedance. This results support that the vias placed at the edge is more effective than the center ones in case that the noise source placed out of area-fill, this results have the same as this paper expected by performance simulation.