Phase/frequency detectors for high-speed PLL applications

Sang O. Jeon, Tae Sik Cheung, Woo-Young Choi

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

Two new phase/frequency detectors (PFDs) are proposed that can overcome the speed and jitter limitations of conventional PFD schemes. One of the proposed circuits has a reset time of 0.32ns and the other a reset time of 0.03ns during the phase-locked loop capture process, according to HSPICE simulation with 0.8μm CMOS process parameters.

Original languageEnglish
Pages (from-to)2120-2121
Number of pages2
JournalElectronics Letters
Volume34
Issue number22
DOIs
Publication statusPublished - 1998 Oct 29

Fingerprint

Phase locked loops
Detectors
Jitter
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Jeon, Sang O. ; Cheung, Tae Sik ; Choi, Woo-Young. / Phase/frequency detectors for high-speed PLL applications. In: Electronics Letters. 1998 ; Vol. 34, No. 22. pp. 2120-2121.
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Phase/frequency detectors for high-speed PLL applications. / Jeon, Sang O.; Cheung, Tae Sik; Choi, Woo-Young.

In: Electronics Letters, Vol. 34, No. 22, 29.10.1998, p. 2120-2121.

Research output: Contribution to journalArticle

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