Physical-Aware approaches for speeding up scan shift operations in SoCs

Taehee Lee, Ik Joon Chang, Chilgee Lee, Joon Sung Yang

Research output: Contribution to journalArticlepeer-review

Abstract

System-on-chip (SoC) designs have a number of flipflops; the more flip-flops an SoC has, the longer the associated scan test application time will be. A scan shift operation accounts for a significant portion of a scan test application time. This paper presents physical-aware approaches for speeding up scan shift operations in SoCs. To improve the speed of a scan shift operation, we propose a layout-aware flip-flop insertion and scan shift operation-aware physical implementation procedure. The proposed combined method of insertion and procedure effectively improves the speed of a scan shift operation. Static timing analyses of state-of-the-art SoC designs show that the proposed approaches help increase the speeds of scan shift operations by up to 4.1 times that reached under a conventional method. The faster scan shift operation speeds help to shorten scan test application times, thus reducing test costs.

Original languageEnglish
Pages (from-to)479-486
Number of pages8
JournalETRI Journal
Volume38
Issue number3
DOIs
Publication statusPublished - 2016 Jun

Bibliographical note

Funding Information:
This research was supported by Basic Science Research Program through the National Research Foundation of Korea funded by the Ministry of Education (NRF-2015R1D1A1A01058856) and in part by the National Research Foundation of Korea (NRF-2013R1A1A1005832).

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Computer Science(all)
  • Electrical and Electronic Engineering

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