PMOS Pass Gate Local Bitline SRAM Architecture with Virtual V_{\mathrm{SS}} for Near-Threshold Operation

Juhyun Park, Tae Woo Oh, Seong Ook Jung

Research output: Contribution to journalArticle

Abstract

In this brief, a pMOS pass gate (PPG) local bitline static random access memory (LB SRAM) architecture is proposed to reduce the read delay and resolve the half-select issue with a small area overhead. Virtual V_{\mathrm {SS}} write assist is included in the architecture to improve write ability. In 22-nm fin-shaped FET (FinFET) technology, the proposed PPG LB architecture achieves an improved read delay and reduced total operation energy by 44% and 65%, respectively, at 0.4 V, compared to the full-swing LB (FSLB) SRAM architecture.

Original languageEnglish
Article number8966589
Pages (from-to)1079-1083
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume28
Issue number4
DOIs
Publication statusPublished - 2020 Apr

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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