Post-bond Repair of Line Faults with Double-bit ECC for 3D Memory

Younwoo Yoo; Hayoung Lee; Seung Ho Shin; Sungho Kang

doi:10.1109/ISOCC53507.2021.9613892

Post-bond Repair of Line Faults with Double-bit ECC for 3D Memory

Younwoo Yoo, Hayoung Lee, Seung Ho Shin, Sungho Kang

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Built in redundancy analysis (BIRA) is used in the manufacturing process for memory yield. However, as the memory density increases, fault occurrence in the memory process is increasing. Thus, it is difficult to handle numerous faults by solely using BIRA. Therefore, the previous studies on using error correction code (ECC) on memory have been actively conducted. In this paper, PRIDE (Post-bond lIne Repair with Double-bit ECC) is proposed. PRIDE uses the double-bit ECC for remaining faults after repairing row lines with the highest number of faults in the post-bond process to achieve high repair rate and reliability in the memory with numerous faults.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2021, ISOCC 2021
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	427-428
Number of pages	2
ISBN (Electronic)	9781665401746
DOIs	https://doi.org/10.1109/ISOCC53507.2021.9613892
Publication status	Published - 2021
Event	18th International System-on-Chip Design Conference, ISOCC 2021 - Jeju Island, Korea, Republic of Duration: 2021 Oct 6 → 2021 Oct 9

Publication series

Name	Proceedings - International SoC Design Conference 2021, ISOCC 2021

Conference

Conference	18th International System-on-Chip Design Conference, ISOCC 2021
Country/Territory	Korea, Republic of
City	Jeju Island
Period	21/10/6 → 21/10/9

Bibliographical note

Funding Information:
This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No. 2019R1A2C3011079).

Publisher Copyright:
© 2021 IEEE.

All Science Journal Classification (ASJC) codes

Computer Networks and Communications
Information Systems
Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ISOCC53507.2021.9613892

Cite this

Yoo, Y., Lee, H., Shin, S. H., & Kang, S. (2021). Post-bond Repair of Line Faults with Double-bit ECC for 3D Memory. In Proceedings - International SoC Design Conference 2021, ISOCC 2021 (pp. 427-428). (Proceedings - International SoC Design Conference 2021, ISOCC 2021). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC53507.2021.9613892

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abstract = "Built in redundancy analysis (BIRA) is used in the manufacturing process for memory yield. However, as the memory density increases, fault occurrence in the memory process is increasing. Thus, it is difficult to handle numerous faults by solely using BIRA. Therefore, the previous studies on using error correction code (ECC) on memory have been actively conducted. In this paper, PRIDE (Post-bond lIne Repair with Double-bit ECC) is proposed. PRIDE uses the double-bit ECC for remaining faults after repairing row lines with the highest number of faults in the post-bond process to achieve high repair rate and reliability in the memory with numerous faults.",

author = "Younwoo Yoo and Hayoung Lee and Shin, {Seung Ho} and Sungho Kang",

note = "Funding Information: This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No. 2019R1A2C3011079). Publisher Copyright: {\textcopyright} 2021 IEEE.; 18th International System-on-Chip Design Conference, ISOCC 2021 ; Conference date: 06-10-2021 Through 09-10-2021",

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doi = "10.1109/ISOCC53507.2021.9613892",

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Yoo, Y, Lee, H, Shin, SH & Kang, S 2021, Post-bond Repair of Line Faults with Double-bit ECC for 3D Memory. in Proceedings - International SoC Design Conference 2021, ISOCC 2021. Proceedings - International SoC Design Conference 2021, ISOCC 2021, Institute of Electrical and Electronics Engineers Inc., pp. 427-428, 18th International System-on-Chip Design Conference, ISOCC 2021, Jeju Island, Korea, Republic of, 21/10/6. https://doi.org/10.1109/ISOCC53507.2021.9613892

Post-bond Repair of Line Faults with Double-bit ECC for 3D Memory. / Yoo, Younwoo; Lee, Hayoung; Shin, Seung Ho et al.

Proceedings - International SoC Design Conference 2021, ISOCC 2021. Institute of Electrical and Electronics Engineers Inc., 2021. p. 427-428 (Proceedings - International SoC Design Conference 2021, ISOCC 2021).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Lee, Hayoung

AU - Shin, Seung Ho

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N1 - Funding Information: This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No. 2019R1A2C3011079). Publisher Copyright: © 2021 IEEE.

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AB - Built in redundancy analysis (BIRA) is used in the manufacturing process for memory yield. However, as the memory density increases, fault occurrence in the memory process is increasing. Thus, it is difficult to handle numerous faults by solely using BIRA. Therefore, the previous studies on using error correction code (ECC) on memory have been actively conducted. In this paper, PRIDE (Post-bond lIne Repair with Double-bit ECC) is proposed. PRIDE uses the double-bit ECC for remaining faults after repairing row lines with the highest number of faults in the post-bond process to achieve high repair rate and reliability in the memory with numerous faults.

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Post-bond Repair of Line Faults with Double-bit ECC for 3D Memory

Abstract

Publication series

Conference

Bibliographical note

All Science Journal Classification (ASJC) codes

Access to Document

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