POSTER: Location-Aware Computation Mapping for Manycore Processors

Orhan Kislal, Jagadish Kotra, Xulong Tang, Mahmut Taylan Kandemir, Myoungsoo Jung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

Employing an on-chip network in a manycore system (to improve scalability) makes the latencies of data accesses issued by a core non-uniform, which significant impact application performance. This paper presents a compiler strategy which involves exposing architecture information to the compiler to enable optimized computation-to-core mapping. Our scheme takes into account the relative positions of (and distances between) cores, last-level caches (LLCs) and memory controllers (MCs) in a manycore system, and generates a mapping of computations to cores with the goal of minimizing the on-chip network traffic. Our experiments of 12 multi-threaded applications reveal that, on average, our approach reduces the on-chip network latency in a 6x6 manycore system by 49.5% in the case of private LLCs and 52.7% in the case of shared LLCs. These improvements translate to the corresponding execution time improvements of 14.8% and 15.2% for the private LLC and shared LLC based systems.

Original languageEnglish
Title of host publicationProceedings - 26th International Conference on Parallel Architectures and Compilation Techniques, PACT 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages138-139
Number of pages2
ISBN (Electronic)9781467395243
DOIs
Publication statusPublished - 2017 Oct 31
Event26th International Conference on Parallel Architectures and Compilation Techniques, PACT 2017 - Portland, United States
Duration: 2017 Sep 92017 Sep 13

Publication series

NameParallel Architectures and Compilation Techniques - Conference Proceedings, PACT
Volume2017-September
ISSN (Print)1089-795X

Other

Other26th International Conference on Parallel Architectures and Compilation Techniques, PACT 2017
CountryUnited States
CityPortland
Period17/9/917/9/13

All Science Journal Classification (ASJC) codes

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture

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    Kislal, O., Kotra, J., Tang, X., Kandemir, M. T., & Jung, M. (2017). POSTER: Location-Aware Computation Mapping for Manycore Processors. In Proceedings - 26th International Conference on Parallel Architectures and Compilation Techniques, PACT 2017 (pp. 138-139). (Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT; Vol. 2017-September). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/PACT.2017.20