Abstract
This paper proposes a power-aware cache block allocation algorithm for the way-selective set-associative cache on embedded systems to reduce energy consumption without additional delay or performance degradation. For this goal, way selection logic and specialized replacement policy are designed to enable only one way of set-associative cache as in the direct-mapped cache. Overall cache access time becomes almost the same as that of conventional set associative cache with accessing additional way selection logic. Because data array can be accessed without waiting for tag comparison, multiplexer delay can be removed totally. The simulation result shows that the proposed architecture can reduce a per access power consumption by 59% over conventional set-associative caches with average 0.06% of negligible performance loss.
| Original language | English |
|---|---|
| Pages (from-to) | 42-47 |
| Number of pages | 6 |
| Journal | Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors |
| Publication status | Published - 2004 Dec 1 |
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All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
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Power-aware deterministic block allocation for low-power way-selective cache structure. / Park, Jung Wook; Park, Gi Ho; Park, Sung Bae; Kim, Shin-Dug.
In: Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, 01.12.2004, p. 42-47.Research output: Contribution to journal › Conference article
TY - JOUR
T1 - Power-aware deterministic block allocation for low-power way-selective cache structure
AU - Park, Jung Wook
AU - Park, Gi Ho
AU - Park, Sung Bae
AU - Kim, Shin-Dug
PY - 2004/12/1
Y1 - 2004/12/1
N2 - This paper proposes a power-aware cache block allocation algorithm for the way-selective set-associative cache on embedded systems to reduce energy consumption without additional delay or performance degradation. For this goal, way selection logic and specialized replacement policy are designed to enable only one way of set-associative cache as in the direct-mapped cache. Overall cache access time becomes almost the same as that of conventional set associative cache with accessing additional way selection logic. Because data array can be accessed without waiting for tag comparison, multiplexer delay can be removed totally. The simulation result shows that the proposed architecture can reduce a per access power consumption by 59% over conventional set-associative caches with average 0.06% of negligible performance loss.
AB - This paper proposes a power-aware cache block allocation algorithm for the way-selective set-associative cache on embedded systems to reduce energy consumption without additional delay or performance degradation. For this goal, way selection logic and specialized replacement policy are designed to enable only one way of set-associative cache as in the direct-mapped cache. Overall cache access time becomes almost the same as that of conventional set associative cache with accessing additional way selection logic. Because data array can be accessed without waiting for tag comparison, multiplexer delay can be removed totally. The simulation result shows that the proposed architecture can reduce a per access power consumption by 59% over conventional set-associative caches with average 0.06% of negligible performance loss.
UR - http://www.scopus.com/inward/record.url?scp=17644416840&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=17644416840&partnerID=8YFLogxK
M3 - Conference article
SP - 42
EP - 47
JO - Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
JF - Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
SN - 1063-6404
ER -