Power-Gated 9T SRAM Cell for Low-Energy Operation

Tae Woo Oh; Hanwool Jeong; Kyoman Kang; Juhyun Park; Younghwi Yang; Seong Ook Jung

doi:10.1109/TVLSI.2016.2623601

Power-Gated 9T SRAM Cell for Low-Energy Operation

Tae Woo Oh, Hanwool Jeong, Kyoman Kang, Juhyun Park, Younghwi Yang, Seong Ook Jung

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article

28 Citations (Scopus)

Abstract

This brief proposes a novel power-gated 9T (PG9T) static random access memory (SRAM) cell that uses a read-decoupled access buffer and power-gating transistors to execute reliable read and write operations. The proposed 9T SRAM cell uses bit interleaving to achieve soft error immunity and utilizes a column-based virtual V_SS signal to eliminate unnecessary bitline discharges in the unselected columns, thereby reducing the energy consumption. In a 22-nm FinFET technology, the proposed PG9T SRAM cell has a minimum operating voltage of 0.32 V while achieving the 6σ read stability yield. Compared with the previously proposed 9T SRAM cell, the proposed cell consumes 45% and 17% less energy per read and write operation, respectively, at the minimum operating voltage, and has a 12% smaller bit cell area.

Original language	English
Article number	7747478
Pages (from-to)	1183-1187
Number of pages	5
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	25
Issue number	3
DOIs	https://doi.org/10.1109/TVLSI.2016.2623601
Publication status	Published - 2017 Mar

All Science Journal Classification (ASJC) codes

Software
Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/TVLSI.2016.2623601

Fingerprint Dive into the research topics of 'Power-Gated 9T SRAM Cell for Low-Energy Operation'. Together they form a unique fingerprint.

Cite this

Oh, T. W., Jeong, H., Kang, K., Park, J., Yang, Y., & Jung, S. O. (2017). Power-Gated 9T SRAM Cell for Low-Energy Operation. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25(3), 1183-1187. [7747478]. https://doi.org/10.1109/TVLSI.2016.2623601

@article{3faa1b6f89324f72be0c73e46025ccc7,

title = "Power-Gated 9T SRAM Cell for Low-Energy Operation",

abstract = "This brief proposes a novel power-gated 9T (PG9T) static random access memory (SRAM) cell that uses a read-decoupled access buffer and power-gating transistors to execute reliable read and write operations. The proposed 9T SRAM cell uses bit interleaving to achieve soft error immunity and utilizes a column-based virtual VSS signal to eliminate unnecessary bitline discharges in the unselected columns, thereby reducing the energy consumption. In a 22-nm FinFET technology, the proposed PG9T SRAM cell has a minimum operating voltage of 0.32 V while achieving the 6σ read stability yield. Compared with the previously proposed 9T SRAM cell, the proposed cell consumes 45% and 17% less energy per read and write operation, respectively, at the minimum operating voltage, and has a 12% smaller bit cell area.",

author = "Oh, {Tae Woo} and Hanwool Jeong and Kyoman Kang and Juhyun Park and Younghwi Yang and Jung, {Seong Ook}",

year = "2017",

month = mar,

doi = "10.1109/TVLSI.2016.2623601",

language = "English",

volume = "25",

pages = "1183--1187",

journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",

issn = "1063-8210",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "3",

}

TY - JOUR

T1 - Power-Gated 9T SRAM Cell for Low-Energy Operation

AU - Oh, Tae Woo

AU - Jeong, Hanwool

AU - Kang, Kyoman

AU - Park, Juhyun

AU - Yang, Younghwi

AU - Jung, Seong Ook

PY - 2017/3

Y1 - 2017/3

N2 - This brief proposes a novel power-gated 9T (PG9T) static random access memory (SRAM) cell that uses a read-decoupled access buffer and power-gating transistors to execute reliable read and write operations. The proposed 9T SRAM cell uses bit interleaving to achieve soft error immunity and utilizes a column-based virtual VSS signal to eliminate unnecessary bitline discharges in the unselected columns, thereby reducing the energy consumption. In a 22-nm FinFET technology, the proposed PG9T SRAM cell has a minimum operating voltage of 0.32 V while achieving the 6σ read stability yield. Compared with the previously proposed 9T SRAM cell, the proposed cell consumes 45% and 17% less energy per read and write operation, respectively, at the minimum operating voltage, and has a 12% smaller bit cell area.

AB - This brief proposes a novel power-gated 9T (PG9T) static random access memory (SRAM) cell that uses a read-decoupled access buffer and power-gating transistors to execute reliable read and write operations. The proposed 9T SRAM cell uses bit interleaving to achieve soft error immunity and utilizes a column-based virtual VSS signal to eliminate unnecessary bitline discharges in the unselected columns, thereby reducing the energy consumption. In a 22-nm FinFET technology, the proposed PG9T SRAM cell has a minimum operating voltage of 0.32 V while achieving the 6σ read stability yield. Compared with the previously proposed 9T SRAM cell, the proposed cell consumes 45% and 17% less energy per read and write operation, respectively, at the minimum operating voltage, and has a 12% smaller bit cell area.

UR - http://www.scopus.com/inward/record.url?scp=84996866130&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84996866130&partnerID=8YFLogxK

U2 - 10.1109/TVLSI.2016.2623601

DO - 10.1109/TVLSI.2016.2623601

M3 - Article

AN - SCOPUS:84996866130

VL - 25

SP - 1183

EP - 1187

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

SN - 1063-8210

IS - 3

M1 - 7747478

ER -