Power-Gated 9T SRAM Cell for Low-Energy Operation

Tae Woo Oh; Hanwool Jeong; Kyoman Kang; Juhyun Park; Younghwi Yang; Seong Ook Jung

doi:10.1109/TVLSI.2016.2623601

Power-Gated 9T SRAM Cell for Low-Energy Operation

Tae Woo Oh, Hanwool Jeong, Kyoman Kang, Juhyun Park, Younghwi Yang, Seong Ook Jung

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

32 Citations (Scopus)

Abstract

This brief proposes a novel power-gated 9T (PG9T) static random access memory (SRAM) cell that uses a read-decoupled access buffer and power-gating transistors to execute reliable read and write operations. The proposed 9T SRAM cell uses bit interleaving to achieve soft error immunity and utilizes a column-based virtual V_SS signal to eliminate unnecessary bitline discharges in the unselected columns, thereby reducing the energy consumption. In a 22-nm FinFET technology, the proposed PG9T SRAM cell has a minimum operating voltage of 0.32 V while achieving the 6σ read stability yield. Compared with the previously proposed 9T SRAM cell, the proposed cell consumes 45% and 17% less energy per read and write operation, respectively, at the minimum operating voltage, and has a 12% smaller bit cell area.

Original language	English
Article number	7747478
Pages (from-to)	1183-1187
Number of pages	5
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	25
Issue number	3
DOIs	https://doi.org/10.1109/TVLSI.2016.2623601
Publication status	Published - 2017 Mar

Bibliographical note

Publisher Copyright:
© 2016 IEEE.

All Science Journal Classification (ASJC) codes

Software
Hardware and Architecture
Electrical and Electronic Engineering

UN SDGs

This output contributes to the following Sustainable Development Goal(s)

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abstract = "This brief proposes a novel power-gated 9T (PG9T) static random access memory (SRAM) cell that uses a read-decoupled access buffer and power-gating transistors to execute reliable read and write operations. The proposed 9T SRAM cell uses bit interleaving to achieve soft error immunity and utilizes a column-based virtual VSS signal to eliminate unnecessary bitline discharges in the unselected columns, thereby reducing the energy consumption. In a 22-nm FinFET technology, the proposed PG9T SRAM cell has a minimum operating voltage of 0.32 V while achieving the 6σ read stability yield. Compared with the previously proposed 9T SRAM cell, the proposed cell consumes 45% and 17% less energy per read and write operation, respectively, at the minimum operating voltage, and has a 12% smaller bit cell area.",

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AU - Yang, Younghwi

AU - Jung, Seong Ook

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Power-Gated 9T SRAM Cell for Low-Energy Operation

Abstract

Bibliographical note

All Science Journal Classification (ASJC) codes

UN SDGs

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