In this paper, to the aim of more than 10 dB power noise suppression, investigation of spiral resonators applied in the vicinity of the practical high-speed digital circuit. Their performances are characterized in terms of their capability to effectively suppress simultaneous switching noise in the frequency region of interest with small occupying area on the power distribution network. As a starting point, the maximum order of harmonic up to which the most energy of clock signal is concentrated is estimated by power spectrum analysis for practical high-speed digital circuit. Then, design parameters of a spiral resonator such as the width, the gap and the number of turns were simulated to determine the suppression level and bandwitdh in DDR3 signal. Numerical results are given in order to illustrate the effectiveness of noise suppression of spiral resonator and to validate the theoretical analysis.