PowerViP: SoC power estimation framework at transaction level

Ikhwan Lee, Hyunsuk Kim, Peng Yang, Sungjoo Yoo, Eui Young Chung, Kyu Myung Choi, Jeong Taek Kong, Soo Kwan Eo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

50 Citations (Scopus)

Abstract

In this work, we propose a SoC power estimation framework built on our system-level1 simulation environment. Our framework provides designers with the system-level power profile in a cycle-accurate manner. We target the framework to run fast and accurately, which is enabled by adopting different modeling techniques depending on the power characteristics of various IP blocks. The framework can be applied to any target SoC design.

Original languageEnglish
Title of host publicationProceedings of the ASP-DAC 2006
Subtitle of host publicationAsia and South Pacific Design Automation Conference 2006
Pages551-558
Number of pages8
Publication statusPublished - 2006 Sep 19
EventASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006 - Yokohama, Japan
Duration: 2006 Jan 242006 Jan 27

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume2006

Other

OtherASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006
CountryJapan
CityYokohama
Period06/1/2406/1/27

    Fingerprint

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Cite this

Lee, I., Kim, H., Yang, P., Yoo, S., Chung, E. Y., Choi, K. M., Kong, J. T., & Eo, S. K. (2006). PowerViP: SoC power estimation framework at transaction level. In Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006 (pp. 551-558). [1594743] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2006).