Practice and experience of an embedded processor core modeling

Gi Ho Park, Woo Chung Sung, Han Jong Kim, Jung Bin Im, Jung Wook Park, Shin Dug Kim, Sung Bae Park

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents our experience in developing an embedded processor core model for an SOC design. We developed an ARM1136 processor simulation environment based on the ARM's MaxCore tool and the SimpleScaclar simulator. A MaxCore ARM1136 instruction accurate (IA) model is developed to support application programmers for the writing application programs from the early design stage. The MaxCore ARM1136 processor model supports all ARMv4, ARMv5TE and ARM v6 instruction sets with 418 LISA instructions. This MaxCore IA Model can be integrated with the ARM's MaxSim system level design environment to develop application softwares and perform architecture explorations. A SimpleScalar ARM1136 cycle accurate (CA) model is also developed by enhancing the existing SimpleScalar-ARM version in the SimpleScalar 3.0. Most important micro-architectural features of ARM1136 processor are implemented in the enhanced SimpleScalar simulator. The accuracy of the developed SimpleScalar-ARM 1136 simulator is about 97% compared to ARM 1136 RTL simulation with the Dhrystone benchmark (100 iterations).

Original languageEnglish
Title of host publicationHigh Performance Computing and Communications - Second International Conference, HPCC 2006, Proceedings
PublisherSpringer Verlag
Pages621-630
Number of pages10
Volume4208 LNCS
ISBN (Print)3540393684, 9783540393689
Publication statusPublished - 2006 Jan 1
Event2nd International Conference on High Performance Computing and Communications, HPCC 2006 - Munich, Germany
Duration: 2006 Sep 132006 Sep 15

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume4208 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Other

Other2nd International Conference on High Performance Computing and Communications, HPCC 2006
CountryGermany
CityMunich
Period06/9/1306/9/15

Fingerprint

Embedded Processor
Modeling
Simulator
Simulators
Application programs
Model
Simulation Environment
Experience
Benchmark
Iteration
Cycle
Software
Design
Simulation

All Science Journal Classification (ASJC) codes

  • Theoretical Computer Science
  • Computer Science(all)

Cite this

Park, G. H., Sung, W. C., Kim, H. J., Im, J. B., Park, J. W., Kim, S. D., & Park, S. B. (2006). Practice and experience of an embedded processor core modeling. In High Performance Computing and Communications - Second International Conference, HPCC 2006, Proceedings (Vol. 4208 LNCS, pp. 621-630). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 4208 LNCS). Springer Verlag.
Park, Gi Ho ; Sung, Woo Chung ; Kim, Han Jong ; Im, Jung Bin ; Park, Jung Wook ; Kim, Shin Dug ; Park, Sung Bae. / Practice and experience of an embedded processor core modeling. High Performance Computing and Communications - Second International Conference, HPCC 2006, Proceedings. Vol. 4208 LNCS Springer Verlag, 2006. pp. 621-630 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).
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abstract = "This paper presents our experience in developing an embedded processor core model for an SOC design. We developed an ARM1136 processor simulation environment based on the ARM's MaxCore tool and the SimpleScaclar simulator. A MaxCore ARM1136 instruction accurate (IA) model is developed to support application programmers for the writing application programs from the early design stage. The MaxCore ARM1136 processor model supports all ARMv4, ARMv5TE and ARM v6 instruction sets with 418 LISA instructions. This MaxCore IA Model can be integrated with the ARM's MaxSim system level design environment to develop application softwares and perform architecture explorations. A SimpleScalar ARM1136 cycle accurate (CA) model is also developed by enhancing the existing SimpleScalar-ARM version in the SimpleScalar 3.0. Most important micro-architectural features of ARM1136 processor are implemented in the enhanced SimpleScalar simulator. The accuracy of the developed SimpleScalar-ARM 1136 simulator is about 97{\%} compared to ARM 1136 RTL simulation with the Dhrystone benchmark (100 iterations).",
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Park, GH, Sung, WC, Kim, HJ, Im, JB, Park, JW, Kim, SD & Park, SB 2006, Practice and experience of an embedded processor core modeling. in High Performance Computing and Communications - Second International Conference, HPCC 2006, Proceedings. vol. 4208 LNCS, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 4208 LNCS, Springer Verlag, pp. 621-630, 2nd International Conference on High Performance Computing and Communications, HPCC 2006, Munich, Germany, 06/9/13.

Practice and experience of an embedded processor core modeling. / Park, Gi Ho; Sung, Woo Chung; Kim, Han Jong; Im, Jung Bin; Park, Jung Wook; Kim, Shin Dug; Park, Sung Bae.

High Performance Computing and Communications - Second International Conference, HPCC 2006, Proceedings. Vol. 4208 LNCS Springer Verlag, 2006. p. 621-630 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 4208 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Park GH, Sung WC, Kim HJ, Im JB, Park JW, Kim SD et al. Practice and experience of an embedded processor core modeling. In High Performance Computing and Communications - Second International Conference, HPCC 2006, Proceedings. Vol. 4208 LNCS. Springer Verlag. 2006. p. 621-630. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).