Process technology for 1 giga-bit DRAM

K. P. Lee, Y. S. Park, D. H. Ko, C. S. Hwang, C. J. Kang, K. Y. Lee, J. S. Kim, J. K. Park, B. H. Roh, J. Y. Lee, B. C. Kim, J. H. Lee, K. N. Kim, J. W. Park, J. G. Lee

Research output: Contribution to journalConference articlepeer-review

31 Citations (Scopus)


In this paper, we present a giga bit density DRAM technology based on the state-of-the-art technologies. A DRAM with 1 giga bit density design rule is fabricated featuring Shallow Trench Isolation (STI), TiSix gate, Self Aligned Contact (SAC), and simple stack capacitor cell using (Ba,Sr)TiO3 (BST) as a dielectric material. A reliable and highly manufacturable process is established which satisfies the stringent requirement for the next generation memory devices such as 1 Gbit DRAM and beyond.

Original languageEnglish
Pages (from-to)907-910
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
Publication statusPublished - 1995
EventProceedings of the 1995 International Electron Devices Meeting, IEDM'95 - Washington, DC, USA
Duration: 1995 Dec 101995 Dec 13

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Materials Chemistry
  • Electrical and Electronic Engineering


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