Process technology for 1 giga-bit DRAM

K. P. Lee; Y. S. Park; D. H. Ko; C. S. Hwang; C. J. Kang; K. Y. Lee; J. S. Kim; J. K. Park; B. H. Roh; J. Y. Lee; B. C. Kim; J. H. Lee; K. N. Kim; J. W. Park; J. G. Lee

Process technology for 1 giga-bit DRAM

K. P. Lee, Y. S. Park, D. H. Ko, C. S. Hwang, C. J. Kang, K. Y. Lee, J. S. Kim, J. K. Park, B. H. Roh, J. Y. Lee, B. C. Kim, J. H. Lee, K. N. Kim, J. W. Park, J. G. Lee

Department of Materials Science and Engineering

Research output: Contribution to journal › Conference article › peer-review

31 Citations (Scopus)

Abstract

In this paper, we present a giga bit density DRAM technology based on the state-of-the-art technologies. A DRAM with 1 giga bit density design rule is fabricated featuring Shallow Trench Isolation (STI), TiSi_x gate, Self Aligned Contact (SAC), and simple stack capacitor cell using (Ba,Sr)TiO₃ (BST) as a dielectric material. A reliable and highly manufacturable process is established which satisfies the stringent requirement for the next generation memory devices such as 1 Gbit DRAM and beyond.

Original language	English
Pages (from-to)	907-910
Number of pages	4
Journal	Technical Digest - International Electron Devices Meeting
Publication status	Published - 1995
Event	Proceedings of the 1995 International Electron Devices Meeting, IEDM'95 - Washington, DC, USA Duration: 1995 Dec 10 → 1995 Dec 13

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Materials Chemistry
Electrical and Electronic Engineering

Cite this

@article{24e9f15982d245779ac032a1f4257c4a,

title = "Process technology for 1 giga-bit DRAM",

abstract = "In this paper, we present a giga bit density DRAM technology based on the state-of-the-art technologies. A DRAM with 1 giga bit density design rule is fabricated featuring Shallow Trench Isolation (STI), TiSix gate, Self Aligned Contact (SAC), and simple stack capacitor cell using (Ba,Sr)TiO3 (BST) as a dielectric material. A reliable and highly manufacturable process is established which satisfies the stringent requirement for the next generation memory devices such as 1 Gbit DRAM and beyond.",

author = "Lee, {K. P.} and Park, {Y. S.} and Ko, {D. H.} and Hwang, {C. S.} and Kang, {C. J.} and Lee, {K. Y.} and Kim, {J. S.} and Park, {J. K.} and Roh, {B. H.} and Lee, {J. Y.} and Kim, {B. C.} and Lee, {J. H.} and Kim, {K. N.} and Park, {J. W.} and Lee, {J. G.}",

year = "1995",

language = "English",

pages = "907--910",

journal = "Technical Digest - International Electron Devices Meeting",

issn = "0163-1918",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the 1995 International Electron Devices Meeting, IEDM'95 ; Conference date: 10-12-1995 Through 13-12-1995",

}

TY - JOUR

T1 - Process technology for 1 giga-bit DRAM

AU - Lee, K. P.

AU - Park, Y. S.

AU - Ko, D. H.

AU - Hwang, C. S.

AU - Kang, C. J.

AU - Lee, K. Y.

AU - Kim, J. S.

AU - Park, J. K.

AU - Roh, B. H.

AU - Lee, J. Y.

AU - Kim, B. C.

AU - Lee, J. H.

AU - Kim, K. N.

AU - Park, J. W.

AU - Lee, J. G.

PY - 1995

Y1 - 1995

N2 - In this paper, we present a giga bit density DRAM technology based on the state-of-the-art technologies. A DRAM with 1 giga bit density design rule is fabricated featuring Shallow Trench Isolation (STI), TiSix gate, Self Aligned Contact (SAC), and simple stack capacitor cell using (Ba,Sr)TiO3 (BST) as a dielectric material. A reliable and highly manufacturable process is established which satisfies the stringent requirement for the next generation memory devices such as 1 Gbit DRAM and beyond.

AB - In this paper, we present a giga bit density DRAM technology based on the state-of-the-art technologies. A DRAM with 1 giga bit density design rule is fabricated featuring Shallow Trench Isolation (STI), TiSix gate, Self Aligned Contact (SAC), and simple stack capacitor cell using (Ba,Sr)TiO3 (BST) as a dielectric material. A reliable and highly manufacturable process is established which satisfies the stringent requirement for the next generation memory devices such as 1 Gbit DRAM and beyond.

UR - http://www.scopus.com/inward/record.url?scp=0029547112&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0029547112&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0029547112

SN - 0163-1918

SP - 907

EP - 910

JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

T2 - Proceedings of the 1995 International Electron Devices Meeting, IEDM'95

Y2 - 10 December 1995 through 13 December 1995

ER -

Process technology for 1 giga-bit DRAM

Abstract

All Science Journal Classification (ASJC) codes

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