Abstract
Bridge faults are important that cause a reliability concern. Since process variation affects the bridge faults, it should be considered for bridge fault analysis. This paper proposes a new analysis method for resistive bridge faults considering process variation. The proposed method analyzes defect coverage for resistive bridge faults by using circuit level modeling. The proposed method uses the lower level analysis and it reduces redundant test patterns for bridge test.
Original language | English |
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Title of host publication | ISOCC 2016 - International SoC Design Conference |
Subtitle of host publication | Smart SoC for Intelligent Things |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 147-148 |
Number of pages | 2 |
ISBN (Electronic) | 9781467393089 |
DOIs | |
Publication status | Published - 2016 Dec 27 |
Event | 13th International SoC Design Conference, ISOCC 2016 - Jeju, Korea, Republic of Duration: 2016 Oct 23 → 2016 Oct 26 |
Publication series
Name | ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things |
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Other
Other | 13th International SoC Design Conference, ISOCC 2016 |
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Country/Territory | Korea, Republic of |
City | Jeju |
Period | 16/10/23 → 16/10/26 |
Bibliographical note
Publisher Copyright:© 2016 IEEE.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
- Instrumentation