Abstract
Thermal management is one of the critical issues in 3D many-core processors design. 3D many-core floorplanning has so far focused on only the configuration of cores and memories across layers. However, 3D floorplanning should also take die stack ordering into account because the characteristics of dies may vary due to growing process variations. A new 3D floorplanning approach which covers die stack ordering is proposed. The evaluation shows that peak steady state temperature is reduced by about 2 K without any overhead in manufacturing process.
| Original language | English |
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| Title of host publication | 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012 |
| Pages | 193-196 |
| Number of pages | 4 |
| DOIs | |
| Publication status | Published - 2012 |
| Event | 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012 - Taipei, Taiwan, Province of China Duration: 2012 Dec 9 → 2012 Dec 11 |
Publication series
| Name | 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012 |
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Other
| Other | 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012 |
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| Country | Taiwan, Province of China |
| City | Taipei |
| Period | 12/12/9 → 12/12/11 |
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
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Cite this
Hong, H., Lim, J., & Kang, S. (2012). Process variation-aware floorplanning for 3D many-core processors. In 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012 (pp. 193-196). [6469421] (2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012). https://doi.org/10.1109/EDAPS.2012.6469421