Process variation-aware floorplanning for 3D many-core processors

Hyejeong Hong, Jaeil Lim, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Thermal management is one of the critical issues in 3D many-core processors design. 3D many-core floorplanning has so far focused on only the configuration of cores and memories across layers. However, 3D floorplanning should also take die stack ordering into account because the characteristics of dies may vary due to growing process variations. A new 3D floorplanning approach which covers die stack ordering is proposed. The evaluation shows that peak steady state temperature is reduced by about 2 K without any overhead in manufacturing process.

Original languageEnglish
Title of host publication2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012
Pages193-196
Number of pages4
DOIs
Publication statusPublished - 2012 Dec 1
Event2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012 - Taipei, Taiwan, Province of China
Duration: 2012 Dec 92012 Dec 11

Other

Other2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012
CountryTaiwan, Province of China
CityTaipei
Period12/12/912/12/11

Fingerprint

Temperature control
Data storage equipment
Temperature

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Hong, H., Lim, J., & Kang, S. (2012). Process variation-aware floorplanning for 3D many-core processors. In 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012 (pp. 193-196). [6469421] https://doi.org/10.1109/EDAPS.2012.6469421
Hong, Hyejeong ; Lim, Jaeil ; Kang, Sungho. / Process variation-aware floorplanning for 3D many-core processors. 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012. 2012. pp. 193-196
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Hong, H, Lim, J & Kang, S 2012, Process variation-aware floorplanning for 3D many-core processors. in 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012., 6469421, pp. 193-196, 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012, Taipei, Taiwan, Province of China, 12/12/9. https://doi.org/10.1109/EDAPS.2012.6469421

Process variation-aware floorplanning for 3D many-core processors. / Hong, Hyejeong; Lim, Jaeil; Kang, Sungho.

2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012. 2012. p. 193-196 6469421.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Hong H, Lim J, Kang S. Process variation-aware floorplanning for 3D many-core processors. In 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012. 2012. p. 193-196. 6469421 https://doi.org/10.1109/EDAPS.2012.6469421