Abstract
Thermal management is one of the critical issues in 3D many-core processors design. 3D many-core floorplanning has so far focused on only the configuration of cores and memories across layers. However, 3D floorplanning should also take die stack ordering into account because the characteristics of dies may vary due to growing process variations. A new 3D floorplanning approach which covers die stack ordering is proposed. The evaluation shows that peak steady state temperature is reduced by about 2 K without any overhead in manufacturing process.
| Original language | English |
|---|---|
| Title of host publication | 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012 |
| Pages | 193-196 |
| Number of pages | 4 |
| DOIs | |
| Publication status | Published - 2012 Dec 1 |
| Event | 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012 - Taipei, Taiwan, Province of China Duration: 2012 Dec 9 → 2012 Dec 11 |
Other
| Other | 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012 |
|---|---|
| Country | Taiwan, Province of China |
| City | Taipei |
| Period | 12/12/9 → 12/12/11 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
Cite this
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Process variation-aware floorplanning for 3D many-core processors. / Hong, Hyejeong; Lim, Jaeil; Kang, Sungho.
2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012. 2012. p. 193-196 6469421.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Process variation-aware floorplanning for 3D many-core processors
AU - Hong, Hyejeong
AU - Lim, Jaeil
AU - Kang, Sungho
PY - 2012/12/1
Y1 - 2012/12/1
N2 - Thermal management is one of the critical issues in 3D many-core processors design. 3D many-core floorplanning has so far focused on only the configuration of cores and memories across layers. However, 3D floorplanning should also take die stack ordering into account because the characteristics of dies may vary due to growing process variations. A new 3D floorplanning approach which covers die stack ordering is proposed. The evaluation shows that peak steady state temperature is reduced by about 2 K without any overhead in manufacturing process.
AB - Thermal management is one of the critical issues in 3D many-core processors design. 3D many-core floorplanning has so far focused on only the configuration of cores and memories across layers. However, 3D floorplanning should also take die stack ordering into account because the characteristics of dies may vary due to growing process variations. A new 3D floorplanning approach which covers die stack ordering is proposed. The evaluation shows that peak steady state temperature is reduced by about 2 K without any overhead in manufacturing process.
UR - http://www.scopus.com/inward/record.url?scp=84875524635&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84875524635&partnerID=8YFLogxK
U2 - 10.1109/EDAPS.2012.6469421
DO - 10.1109/EDAPS.2012.6469421
M3 - Conference contribution
SN - 9781467314435
SP - 193
EP - 196
BT - 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012
ER -