A multiphase delay locked loop (DLL) that can calibrate the interphase error and guarantee the 50% duty cycle of the output clock of the DLL is presented. The proposed process variation calibration architecture is implemented without the need for complex circuitry because it calibrates the phase error using a simple delay averaging operation among four 90° shifters. In addition, a loop-embedded duty cycle corrector is implemented with extremely small power and area requirements by adopting feedforward and feedback paths. Finally, a sense-amplifier-based phase detector is proposed for reducing dithering jitter. The proposed DLL is fabricated using a 0.13-μm CMOS process. For the seven test chips analyzed, the proposed DLL had a maximum phase error of 1.8° and a duty cycle error of 0.97% at 800 MHz.
|Number of pages||5|
|Journal||IEEE Transactions on Circuits and Systems II: Express Briefs|
|Publication status||Published - 2014 Jan|
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering