Process-variation-calibrated multiphase delay locked loop with a loop-embedded duty cycle corrector

Kyungho Ryu, Dong Hoon Jung, Seong Ook Jung

Research output: Contribution to journalArticle

16 Citations (Scopus)

Abstract

A multiphase delay locked loop (DLL) that can calibrate the interphase error and guarantee the 50% duty cycle of the output clock of the DLL is presented. The proposed process variation calibration architecture is implemented without the need for complex circuitry because it calibrates the phase error using a simple delay averaging operation among four 90° shifters. In addition, a loop-embedded duty cycle corrector is implemented with extremely small power and area requirements by adopting feedforward and feedback paths. Finally, a sense-amplifier-based phase detector is proposed for reducing dithering jitter. The proposed DLL is fabricated using a 0.13-μm CMOS process. For the seven test chips analyzed, the proposed DLL had a maximum phase error of 1.8° and a duty cycle error of 0.97% at 800 MHz.

Original languageEnglish
Article number6678577
Pages (from-to)1-5
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume61
Issue number1
DOIs
Publication statusPublished - 2014 Jan 1

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Jitter
Clocks
Calibration
Detectors
Feedback

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

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abstract = "A multiphase delay locked loop (DLL) that can calibrate the interphase error and guarantee the 50{\%} duty cycle of the output clock of the DLL is presented. The proposed process variation calibration architecture is implemented without the need for complex circuitry because it calibrates the phase error using a simple delay averaging operation among four 90° shifters. In addition, a loop-embedded duty cycle corrector is implemented with extremely small power and area requirements by adopting feedforward and feedback paths. Finally, a sense-amplifier-based phase detector is proposed for reducing dithering jitter. The proposed DLL is fabricated using a 0.13-μm CMOS process. For the seven test chips analyzed, the proposed DLL had a maximum phase error of 1.8° and a duty cycle error of 0.97{\%} at 800 MHz.",
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Process-variation-calibrated multiphase delay locked loop with a loop-embedded duty cycle corrector. / Ryu, Kyungho; Jung, Dong Hoon; Jung, Seong Ook.

In: IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 61, No. 1, 6678577, 01.01.2014, p. 1-5.

Research output: Contribution to journalArticle

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