Process variation tolerant all-digital 90° phase shift DLL for DDR3 interface

Heechai Kang, Kyungho Ryu, Dong Hoon Jung, Donghwan Lee, Won Lee, Suho Kim, Jongryun Choi, Seong Ook Jung

Research output: Contribution to journalArticlepeer-review

25 Citations (Scopus)


An all-digital 90° phase shift delay lock loop (DLL) is presented, which is robust against the delay mismatch caused by process variation. Each of the four 90° phase shift blocks accurately aligns its output to a 90° shifted phase using its own ring oscillator and locking delay code. It is analytically proved that the phase shift accuracy of the proposed 90° phase shift block is always higher than that of the conventional all-digital 90° phase shift DLL. The harmonic locking problem is prevented by a ring oscillator and a counter. An area-efficient binary-to-thermometer converter is proposed to reduce the area overhead caused by the delay-line control logic. A fast operating frequency with a finer resolution is achieved through the fine delay range selector and the resistance controlled fine delay unit. The proposed 90° phase shift DLL is implemented using a 45-nm CMOS process. The phase shift accuracy errors at the 90° and 270° phases are 0.43° and 1.01° , respectively, when the maximum locking delay code difference between the four 90° phase shift delay lines corresponds to ± 9.97° at 800 MHz. It proves that the DLL corrects the significant phase error caused by process variation. The power consumption is 3.3 mW at 800 MHz.

Original languageEnglish
Article number6179317
Pages (from-to)2186-2196
Number of pages11
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Issue number10
Publication statusPublished - 2012

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


Dive into the research topics of 'Process variation tolerant all-digital 90° phase shift DLL for DDR3 interface'. Together they form a unique fingerprint.

Cite this