Process variation tolerant all-digital multiphase DLL for DDR3 interface

H. C. Kang, K. H. Ryu, D. H. Lee, W. Lee, S. H. Kim, J. R. Choi, S. O. Jung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

An all-digital multiphase DLL is presented that is robust to delay mismatch due to process variation. Each of four 90° phase shift blocks accurately align each phase to 90° delay using its own ring oscillator and locking delay code. Harmonic locking is protected by a ring oscillator and a counter. An area efficient binary to thermometer converter is proposed to diminish the area overhead due to four delay line controllers. An edge combiner is used for duty cycle correction and clock 2x multiplications. The measured large locking delay code difference between four 90° phase shift delay lines in the proposed DLL implemented in 45nm CMOS process, which corresponds to ±31ps at 800MHz, proves that the DLL corrects significant phase error caused by delay mismatch. Phase shift accuracy errors at 90° and 270° phases are 0.43° and 1.01°, respectively, and output frequency is 1.6GHz with 50% duty cycle at 800MHz. Power consumption is 3.3mW at 800MHz.

Original languageEnglish
Title of host publicationIEEE Custom Integrated Circuits Conference 2010, CICC 2010
DOIs
Publication statusPublished - 2010 Dec 13
Event32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010 - San Jose, CA, United States
Duration: 2010 Sep 192010 Sep 22

Other

Other32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010
CountryUnited States
CitySan Jose, CA
Period10/9/1910/9/22

Fingerprint

Phase shift
Electric delay lines
Thermometers
Clocks
Electric power utilization
Controllers

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Kang, H. C., Ryu, K. H., Lee, D. H., Lee, W., Kim, S. H., Choi, J. R., & Jung, S. O. (2010). Process variation tolerant all-digital multiphase DLL for DDR3 interface. In IEEE Custom Integrated Circuits Conference 2010, CICC 2010 [5617474] https://doi.org/10.1109/CICC.2010.5617474
Kang, H. C. ; Ryu, K. H. ; Lee, D. H. ; Lee, W. ; Kim, S. H. ; Choi, J. R. ; Jung, S. O. / Process variation tolerant all-digital multiphase DLL for DDR3 interface. IEEE Custom Integrated Circuits Conference 2010, CICC 2010. 2010.
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Kang, HC, Ryu, KH, Lee, DH, Lee, W, Kim, SH, Choi, JR & Jung, SO 2010, Process variation tolerant all-digital multiphase DLL for DDR3 interface. in IEEE Custom Integrated Circuits Conference 2010, CICC 2010., 5617474, 32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010, San Jose, CA, United States, 10/9/19. https://doi.org/10.1109/CICC.2010.5617474

Process variation tolerant all-digital multiphase DLL for DDR3 interface. / Kang, H. C.; Ryu, K. H.; Lee, D. H.; Lee, W.; Kim, S. H.; Choi, J. R.; Jung, S. O.

IEEE Custom Integrated Circuits Conference 2010, CICC 2010. 2010. 5617474.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Kang HC, Ryu KH, Lee DH, Lee W, Kim SH, Choi JR et al. Process variation tolerant all-digital multiphase DLL for DDR3 interface. In IEEE Custom Integrated Circuits Conference 2010, CICC 2010. 2010. 5617474 https://doi.org/10.1109/CICC.2010.5617474