Protecting caches from soft errors: A microarchitect's perspective

Yohan Ko, Reiley Jeyapaul, Youngbin Kim, Kyoungwoo Lee, Aviral Shrivastava

Research output: Contribution to journalReview articlepeer-review

7 Citations (Scopus)


Soft error is one of the most important design concerns in modern embedded systems with aggressive technology scaling. Among various microarchitectural components in a processor, cache is the most susceptible component to soft errors. Error detection and correction codes are common protection techniques for cache memory due to their design simplicity. In order to design effective protection techniques for caches, it is important to quantitatively estimate the susceptibility of caches without and even with protections. At the architectural level, vulnerability is the metric to quantify the susceptibility of data in caches. However, existing tools and techniques calculate the vulnerability of data in caches through coarse-grained block-level estimation. Further, they ignore common cache protection techniques such as error detection and correction codes. In this article, we demonstrate that our word-level vulnerability estimation is accurate through intensive fault injection campaigns as compared to block-level one. Further, our extensive experiments over benchmark suites reveal several counter-intuitive and interesting results. Parity checking when performed over just reads provides reliable and power-efficient protection than that when performed over both reads and writes. On the other hand, checking error correcting codes only at reads alone can be vulnerable even for single-bit soft errors, while that at both reads and writes provides the perfect reliability.

Original languageEnglish
Article number93
JournalACM Transactions on Embedded Computing Systems
Issue number4
Publication statusPublished - 2017 May

Bibliographical note

Funding Information:
This research was supported in part by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT, and future Planning (NRF-2015R1A2A1A15053435); by Next-Generation Information Computing Development Program through the NRF funded by the Ministry of Science, ICT, and Future Planning (NRF-2015M3C4A7065522); by MSIP under the Research Project on High Performance and Scalable Manycore Operating System (# 14-824-09-011); and by funding from National Science Foundation grants CCF 1055094(CAREER), CCF-0916652, and CNS 1525855.

Publisher Copyright:
© 2017 ACM.

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture


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