Abstract
Soft error is one of the most important design concerns in modern embedded systems with aggressive technology scaling. Among various microarchitectural components in a processor, cache is the most susceptible component to soft errors. Error detection and correction codes are common protection techniques for cache memory due to their design simplicity. In order to design effective protection techniques for caches, it is important to quantitatively estimate the susceptibility of caches without and even with protections. At the architectural level, vulnerability is the metric to quantify the susceptibility of data in caches. However, existing tools and techniques calculate the vulnerability of data in caches through coarse-grained block-level estimation. Further, they ignore common cache protection techniques such as error detection and correction codes. In this article, we demonstrate that our word-level vulnerability estimation is accurate through intensive fault injection campaigns as compared to block-level one. Further, our extensive experiments over benchmark suites reveal several counter-intuitive and interesting results. Parity checking when performed over just reads provides reliable and power-efficient protection than that when performed over both reads and writes. On the other hand, checking error correcting codes only at reads alone can be vulnerable even for single-bit soft errors, while that at both reads and writes provides the perfect reliability.
| Original language | English |
|---|---|
| Article number | 93 |
| Journal | ACM Transactions on Embedded Computing Systems |
| Volume | 16 |
| Issue number | 4 |
| DOIs | |
| Publication status | Published - 2017 May 1 |
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All Science Journal Classification (ASJC) codes
- Software
- Hardware and Architecture
Cite this
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Protecting caches from soft errors : A microarchitect's perspective. / Ko, Yohan; Jeyapaul, Reiley; Kim, Youngbin; Lee, Kyoungwoo; Shrivastava, Aviral.
In: ACM Transactions on Embedded Computing Systems, Vol. 16, No. 4, 93, 01.05.2017.Research output: Contribution to journal › Review article
TY - JOUR
T1 - Protecting caches from soft errors
T2 - A microarchitect's perspective
AU - Ko, Yohan
AU - Jeyapaul, Reiley
AU - Kim, Youngbin
AU - Lee, Kyoungwoo
AU - Shrivastava, Aviral
PY - 2017/5/1
Y1 - 2017/5/1
N2 - Soft error is one of the most important design concerns in modern embedded systems with aggressive technology scaling. Among various microarchitectural components in a processor, cache is the most susceptible component to soft errors. Error detection and correction codes are common protection techniques for cache memory due to their design simplicity. In order to design effective protection techniques for caches, it is important to quantitatively estimate the susceptibility of caches without and even with protections. At the architectural level, vulnerability is the metric to quantify the susceptibility of data in caches. However, existing tools and techniques calculate the vulnerability of data in caches through coarse-grained block-level estimation. Further, they ignore common cache protection techniques such as error detection and correction codes. In this article, we demonstrate that our word-level vulnerability estimation is accurate through intensive fault injection campaigns as compared to block-level one. Further, our extensive experiments over benchmark suites reveal several counter-intuitive and interesting results. Parity checking when performed over just reads provides reliable and power-efficient protection than that when performed over both reads and writes. On the other hand, checking error correcting codes only at reads alone can be vulnerable even for single-bit soft errors, while that at both reads and writes provides the perfect reliability.
AB - Soft error is one of the most important design concerns in modern embedded systems with aggressive technology scaling. Among various microarchitectural components in a processor, cache is the most susceptible component to soft errors. Error detection and correction codes are common protection techniques for cache memory due to their design simplicity. In order to design effective protection techniques for caches, it is important to quantitatively estimate the susceptibility of caches without and even with protections. At the architectural level, vulnerability is the metric to quantify the susceptibility of data in caches. However, existing tools and techniques calculate the vulnerability of data in caches through coarse-grained block-level estimation. Further, they ignore common cache protection techniques such as error detection and correction codes. In this article, we demonstrate that our word-level vulnerability estimation is accurate through intensive fault injection campaigns as compared to block-level one. Further, our extensive experiments over benchmark suites reveal several counter-intuitive and interesting results. Parity checking when performed over just reads provides reliable and power-efficient protection than that when performed over both reads and writes. On the other hand, checking error correcting codes only at reads alone can be vulnerable even for single-bit soft errors, while that at both reads and writes provides the perfect reliability.
UR - http://www.scopus.com/inward/record.url?scp=85019840029&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85019840029&partnerID=8YFLogxK
U2 - 10.1145/3063180
DO - 10.1145/3063180
M3 - Review article
AN - SCOPUS:85019840029
VL - 16
JO - Transactions on Embedded Computing Systems
JF - Transactions on Embedded Computing Systems
SN - 1539-9087
IS - 4
M1 - 93
ER -