Pulsed PMOS sense amplifier for high speed single-ended SRAM

Juhyun Park, Hanwool Jeong, Seongook Jung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In this paper, a pulsed pMOS sense amplifier for single-ended static random access memory (SRAM) at low supply voltage is proposed. Domino logic for single-ended SRAM such as 8T SRAM has a large read delay because a large read bitline swing is required. To improve read delay, previously proposed pseudo nMOS based sense amplifier was proposed. However, it has a large static current, which causes a large energy consumption. With 22-nm FinFET technology, the proposed pulsed pMOS sense amplifier improves read delay by about 80% compared with conventional domino logic and reduces energy consumption by 40% compared with previously proposed pseudo nMOS based sense amplifier.

Original languageEnglish
Title of host publicationInternational Conference on Electronics, Information and Communication, ICEIC 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-4
Number of pages4
Volume2018-January
ISBN (Electronic)9781538647547
DOIs
Publication statusPublished - 2018 Apr 2
Event17th International Conference on Electronics, Information and Communication, ICEIC 2018 - Honolulu, United States
Duration: 2018 Jan 242018 Jan 27

Other

Other17th International Conference on Electronics, Information and Communication, ICEIC 2018
CountryUnited States
CityHonolulu
Period18/1/2418/1/27

Fingerprint

Data storage equipment
Energy utilization
Electric potential
FinFET

All Science Journal Classification (ASJC) codes

  • Information Systems
  • Computer Networks and Communications
  • Computer Science Applications
  • Signal Processing
  • Electrical and Electronic Engineering

Cite this

Park, J., Jeong, H., & Jung, S. (2018). Pulsed PMOS sense amplifier for high speed single-ended SRAM. In International Conference on Electronics, Information and Communication, ICEIC 2018 (Vol. 2018-January, pp. 1-4). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/ELINFOCOM.2018.8330662
Park, Juhyun ; Jeong, Hanwool ; Jung, Seongook. / Pulsed PMOS sense amplifier for high speed single-ended SRAM. International Conference on Electronics, Information and Communication, ICEIC 2018. Vol. 2018-January Institute of Electrical and Electronics Engineers Inc., 2018. pp. 1-4
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abstract = "In this paper, a pulsed pMOS sense amplifier for single-ended static random access memory (SRAM) at low supply voltage is proposed. Domino logic for single-ended SRAM such as 8T SRAM has a large read delay because a large read bitline swing is required. To improve read delay, previously proposed pseudo nMOS based sense amplifier was proposed. However, it has a large static current, which causes a large energy consumption. With 22-nm FinFET technology, the proposed pulsed pMOS sense amplifier improves read delay by about 80{\%} compared with conventional domino logic and reduces energy consumption by 40{\%} compared with previously proposed pseudo nMOS based sense amplifier.",
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Park, J, Jeong, H & Jung, S 2018, Pulsed PMOS sense amplifier for high speed single-ended SRAM. in International Conference on Electronics, Information and Communication, ICEIC 2018. vol. 2018-January, Institute of Electrical and Electronics Engineers Inc., pp. 1-4, 17th International Conference on Electronics, Information and Communication, ICEIC 2018, Honolulu, United States, 18/1/24. https://doi.org/10.23919/ELINFOCOM.2018.8330662

Pulsed PMOS sense amplifier for high speed single-ended SRAM. / Park, Juhyun; Jeong, Hanwool; Jung, Seongook.

International Conference on Electronics, Information and Communication, ICEIC 2018. Vol. 2018-January Institute of Electrical and Electronics Engineers Inc., 2018. p. 1-4.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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N2 - In this paper, a pulsed pMOS sense amplifier for single-ended static random access memory (SRAM) at low supply voltage is proposed. Domino logic for single-ended SRAM such as 8T SRAM has a large read delay because a large read bitline swing is required. To improve read delay, previously proposed pseudo nMOS based sense amplifier was proposed. However, it has a large static current, which causes a large energy consumption. With 22-nm FinFET technology, the proposed pulsed pMOS sense amplifier improves read delay by about 80% compared with conventional domino logic and reduces energy consumption by 40% compared with previously proposed pseudo nMOS based sense amplifier.

AB - In this paper, a pulsed pMOS sense amplifier for single-ended static random access memory (SRAM) at low supply voltage is proposed. Domino logic for single-ended SRAM such as 8T SRAM has a large read delay because a large read bitline swing is required. To improve read delay, previously proposed pseudo nMOS based sense amplifier was proposed. However, it has a large static current, which causes a large energy consumption. With 22-nm FinFET technology, the proposed pulsed pMOS sense amplifier improves read delay by about 80% compared with conventional domino logic and reduces energy consumption by 40% compared with previously proposed pseudo nMOS based sense amplifier.

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Park J, Jeong H, Jung S. Pulsed PMOS sense amplifier for high speed single-ended SRAM. In International Conference on Electronics, Information and Communication, ICEIC 2018. Vol. 2018-January. Institute of Electrical and Electronics Engineers Inc. 2018. p. 1-4 https://doi.org/10.23919/ELINFOCOM.2018.8330662