This paper presents a new SoC (System-on-Chip) test scheduling algorithm. Reducing the test application time is an important issue for a core-based SoC test. In this paper, each core is represented by a rectangle, the height of-which is equal to the TAM width and the width of which is equal to the test time. A 'one-element-exchange' algorithm is used for optimizing the test time of each core and the 'RAIN' scheduling algorithm is used for optimizing the test time of SoC. The RAIN scheduling algorithm uses a sequence pair data structure to represent the placement of rectangles, and obtains the optimized results by inserting into a random position on the sequence pair. The results of the experiments conducted using ITC '02 SoC benchmarks show that the proposed algorithm gives the shortest test application time compared with earlier researches for most of the cases.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering