TY - JOUR
T1 - Ramp slope built-in-self-calibration scheme for single-slope column analog-to-digital converter complementary metal-oxide-semiconductor image sensor
AU - Ham, Seogheon
AU - Jung, Wunki
AU - Lee, Dongmyung
AU - Lee, Yonghee
AU - Han, Gunhee
PY - 2006/2/3
Y1 - 2006/2/3
N2 - The conversion gain of a single-slope analog-to-digital converter (ADC) suffers from the process and frequency variations. This ADC gain variation eventually limits the performance of image signal processing (ISP) in a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS). This paper proposes a ramp slope built-in-self-calibration (BISC) scheme for a CIS. The CIS with the proposed BISC was fabricated with a 0.35-μm CMOS process. The measurement results show that the proposed architecture effectively calibrates the ramp slope against the process and the clock frequency variation. The silicon area overhead is less than 0.7% of the full chip area.
AB - The conversion gain of a single-slope analog-to-digital converter (ADC) suffers from the process and frequency variations. This ADC gain variation eventually limits the performance of image signal processing (ISP) in a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS). This paper proposes a ramp slope built-in-self-calibration (BISC) scheme for a CIS. The CIS with the proposed BISC was fabricated with a 0.35-μm CMOS process. The measurement results show that the proposed architecture effectively calibrates the ramp slope against the process and the clock frequency variation. The silicon area overhead is less than 0.7% of the full chip area.
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U2 - 10.1143/JJAP.45.L201
DO - 10.1143/JJAP.45.L201
M3 - Article
AN - SCOPUS:33745126305
VL - 45
SP - L201-L203
JO - Japanese Journal of Applied Physics, Part 2: Letters
JF - Japanese Journal of Applied Physics, Part 2: Letters
SN - 0021-4922
IS - 4-7
ER -