Ramp slope built-in-self-calibration scheme for single-slope column analog-to-digital converter complementary metal-oxide-semiconductor image sensor

Seogheon Ham, Wunki Jung, Dongmyung Lee, Yonghee Lee, Gunhee Han

Research output: Contribution to journalArticle

4 Citations (Scopus)


The conversion gain of a single-slope analog-to-digital converter (ADC) suffers from the process and frequency variations. This ADC gain variation eventually limits the performance of image signal processing (ISP) in a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS). This paper proposes a ramp slope built-in-self-calibration (BISC) scheme for a CIS. The CIS with the proposed BISC was fabricated with a 0.35-μm CMOS process. The measurement results show that the proposed architecture effectively calibrates the ramp slope against the process and the clock frequency variation. The silicon area overhead is less than 0.7% of the full chip area.

Original languageEnglish
Pages (from-to)L201-L203
JournalJapanese Journal of Applied Physics, Part 2: Letters
Issue number4-7
Publication statusPublished - 2006 Feb 3


All Science Journal Classification (ASJC) codes

  • Engineering(all)
  • Physics and Astronomy (miscellaneous)
  • Physics and Astronomy(all)

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