Ramp slope built-in-self-calibration scheme for single-slope column analog-to-digital converter complementary metal-oxide-semiconductor image sensor

Seogheon Ham; Wunki Jung; Dongmyung Lee; Yonghee Lee; Gunhee Han

doi:10.1143/JJAP.45.L201

Ramp slope built-in-self-calibration scheme for single-slope column analog-to-digital converter complementary metal-oxide-semiconductor image sensor

Seogheon Ham, Wunki Jung, Dongmyung Lee, Yonghee Lee, Gunhee Han

School of Integrated Technology

Research output: Contribution to journal › Article › peer-review

4 Citations (Scopus)

Abstract

The conversion gain of a single-slope analog-to-digital converter (ADC) suffers from the process and frequency variations. This ADC gain variation eventually limits the performance of image signal processing (ISP) in a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS). This paper proposes a ramp slope built-in-self-calibration (BISC) scheme for a CIS. The CIS with the proposed BISC was fabricated with a 0.35-μm CMOS process. The measurement results show that the proposed architecture effectively calibrates the ramp slope against the process and the clock frequency variation. The silicon area overhead is less than 0.7% of the full chip area.

Original language	English
Pages (from-to)	L201-L203
Journal	Japanese Journal of Applied Physics, Part 2: Letters
Volume	45
Issue number	4-7
DOIs	https://doi.org/10.1143/JJAP.45.L201
Publication status	Published - 2006 Feb 3

All Science Journal Classification (ASJC) codes

Engineering(all)
Physics and Astronomy (miscellaneous)
Physics and Astronomy(all)

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10.1143/JJAP.45.L201

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abstract = "The conversion gain of a single-slope analog-to-digital converter (ADC) suffers from the process and frequency variations. This ADC gain variation eventually limits the performance of image signal processing (ISP) in a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS). This paper proposes a ramp slope built-in-self-calibration (BISC) scheme for a CIS. The CIS with the proposed BISC was fabricated with a 0.35-μm CMOS process. The measurement results show that the proposed architecture effectively calibrates the ramp slope against the process and the clock frequency variation. The silicon area overhead is less than 0.7% of the full chip area.",

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Ramp slope built-in-self-calibration scheme for single-slope column analog-to-digital converter complementary metal-oxide-semiconductor image sensor. / Ham, Seogheon; Jung, Wunki; Lee, Dongmyung; Lee, Yonghee; Han, Gunhee.

In: Japanese Journal of Applied Physics, Part 2: Letters, Vol. 45, No. 4-7, 03.02.2006, p. L201-L203.

Research output: Contribution to journal › Article › peer-review

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