The degradation of the read stability and write ability of static random-access memory (SRAM) is becoming a critical problem in deep submicrometer technology. To solve this problem, there are many SRAM cell design options such as preferred cells and assist circuits. In addition, extremely thin silicon-on-insulator (ETSOI) with a buried oxide offers an independent back-gate control. In this paper, previously proposed SRAM back-gate-assist circuit schemes are analyzed. From this, we propose a read-preferred SRAM cell with a write-assist circuit using the back-gate ETSOI. The proposed write-assist circuit minimizes the dynamic power overhead and satisfies a sufficient cell sigma in all cells during the read and write operations.
|Number of pages||7|
|Journal||IEEE Transactions on Electron Devices|
|Publication status||Published - 2012|
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering