Real-time FPGA rectification implementation combined with stereo camera

Junwon Mun; Jaeseok Kim

doi:10.1109/ISCE.2015.7177765

Real-time FPGA rectification implementation combined with stereo camera

Junwon Mun, Jaeseok Kim

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

In this paper, we proposed real-time FPGA-based rectification algorithm implementation combined with stereo camera. Rectification is a necessary pre-required step for stereo matching to align left and right images, including correction of radial distortion. In our experiment, we implemented rectification module in the FPGA combined with stereo camera to verify in video circumstance. As a result, rectification for HD image is processed at 45 fps, with Zynq7020 FPGA.

Original language	English
Title of host publication	2015 International Symposium on Consumer Electronics, ISCE 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781467373654
DOIs	https://doi.org/10.1109/ISCE.2015.7177765
Publication status	Published - 2015 Aug 4
Event	IEEE International Symposium on Consumer Electronics, ISCE 2015 - Madrid, Spain Duration: 2015 Jun 24 → 2015 Jun 26

Publication series

Name	Proceedings of the International Symposium on Consumer Electronics, ISCE
Volume	2015-August

Other

Other	IEEE International Symposium on Consumer Electronics, ISCE 2015
Country	Spain
City	Madrid
Period	15/6/24 → 15/6/26

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

All Science Journal Classification (ASJC) codes

Engineering(all)

Access to Document

10.1109/ISCE.2015.7177765

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title = "Real-time FPGA rectification implementation combined with stereo camera",

abstract = "In this paper, we proposed real-time FPGA-based rectification algorithm implementation combined with stereo camera. Rectification is a necessary pre-required step for stereo matching to align left and right images, including correction of radial distortion. In our experiment, we implemented rectification module in the FPGA combined with stereo camera to verify in video circumstance. As a result, rectification for HD image is processed at 45 fps, with Zynq7020 FPGA.",

author = "Junwon Mun and Jaeseok Kim",

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doi = "10.1109/ISCE.2015.7177765",

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Mun, J & Kim, J 2015, Real-time FPGA rectification implementation combined with stereo camera. in 2015 International Symposium on Consumer Electronics, ISCE 2015., 7177765, Proceedings of the International Symposium on Consumer Electronics, ISCE, vol. 2015-August, Institute of Electrical and Electronics Engineers Inc., IEEE International Symposium on Consumer Electronics, ISCE 2015, Madrid, Spain, 15/6/24. https://doi.org/10.1109/ISCE.2015.7177765

Real-time FPGA rectification implementation combined with stereo camera. / Mun, Junwon; Kim, Jaeseok.

2015 International Symposium on Consumer Electronics, ISCE 2015. Institute of Electrical and Electronics Engineers Inc., 2015. 7177765 (Proceedings of the International Symposium on Consumer Electronics, ISCE; Vol. 2015-August).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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Real-time FPGA rectification implementation combined with stereo camera

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