Artificial intelligence applications have changed the landscape of computer design, driving a search for hardware architecture that can efficiently process large amounts of data. Three-dimensional heterogeneous integration with advanced packaging technologies could be used to improve data bandwidth among sensors, memory and processors. However, such systems are limited by a lack of hardware reconfigurability and the use of conventional von Neumann architectures. Here we report stackable hetero-integrated chips that use optoelectronic device arrays for chip-to-chip communication and neuromorphic cores based on memristor crossbar arrays for highly parallel data processing. With this approach, we create a system with stackable and replaceable chips that can directly classify information from a light-based image source. We also modify this system by inserting a preprogrammed neuromorphic denoising layer that improves the classification performance in a noisy environment. Our reconfigurable three-dimensional hetero-integrated technology can be used to vertically stack a diverse range of functional layers and could provide energy-efficient sensor computing systems for edge computing applications.
|Number of pages||8|
|Publication status||Published - 2022 Jun|
Bibliographical noteFunding Information:
J.-H.K. acknowledges financial support from the Ministry of Trade, Industry and Energy (MOTIE), South Korea, under the Fostering Global Talents for Innovative Growth Program (P0008749) by the Korea Institute for Advancement of Technology (KIAT). The team at MIT acknowledge financial support from the Korea Institute of Science and Technology (KIST) through 2E31550 and the Samsung Global Research Outreach (GRO) Program.
© 2022, The Author(s), under exclusive licence to Springer Nature Limited.
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering