Abstract
Power-aware design is one of the most important areas to be emphasized in multimedia mobile systems, in which data transfers dominate the power consumption. In this paper, we propose a new architecture for motion compensation (MC) of H.264/AVC with power reduction by decreasing the data transfers. For this purpose, a reconfigurable microarchitecture based on data type is proposed for interpolation and it is mapped onto the dedicated motion compensation IP (intellectual property) effectively without sacrificing the performance or the system latency, The original quarter-pel interpolation equation that consists of one or two half-pel interpolations and one averaging operation is designed to have different execution control modes, which result in decreasing memory accesses greatly and maintaining the system efficiency. The simulation result shows that the proposed method could reduce up to 87% of power caused by data transfers over the conventional method in MC module.
| Original language | English |
|---|---|
| Title of host publication | Embedded Software and Systems |
| Subtitle of host publication | Second International Conference, ICESS 2005, Proceedings |
| Pages | 39-49 |
| Number of pages | 11 |
| Volume | 3820 LNCS |
| Publication status | Published - 2005 Dec 1 |
| Event | 2nd International Conference on Embedded Software and Systems, ICESS 2005 - Xi'an, China Duration: 2005 Dec 16 → 2005 Dec 18 |
Publication series
| Name | Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) |
|---|---|
| Volume | 3820 LNCS |
| ISSN (Print) | 0302-9743 |
| ISSN (Electronic) | 1611-3349 |
Other
| Other | 2nd International Conference on Embedded Software and Systems, ICESS 2005 |
|---|---|
| Country | China |
| City | Xi'an |
| Period | 05/12/16 → 05/12/18 |
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All Science Journal Classification (ASJC) codes
- Theoretical Computer Science
- Computer Science(all)
Cite this
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Reconfigurable microarchitecture based system-level dynamic power management SoC platform. / Kim, Cheong Ghil; Jeong, Dae Young; Kim, Byung Gil; Kim, Shin Dug.
Embedded Software and Systems: Second International Conference, ICESS 2005, Proceedings. Vol. 3820 LNCS 2005. p. 39-49 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 3820 LNCS).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Reconfigurable microarchitecture based system-level dynamic power management SoC platform
AU - Kim, Cheong Ghil
AU - Jeong, Dae Young
AU - Kim, Byung Gil
AU - Kim, Shin Dug
PY - 2005/12/1
Y1 - 2005/12/1
N2 - Power-aware design is one of the most important areas to be emphasized in multimedia mobile systems, in which data transfers dominate the power consumption. In this paper, we propose a new architecture for motion compensation (MC) of H.264/AVC with power reduction by decreasing the data transfers. For this purpose, a reconfigurable microarchitecture based on data type is proposed for interpolation and it is mapped onto the dedicated motion compensation IP (intellectual property) effectively without sacrificing the performance or the system latency, The original quarter-pel interpolation equation that consists of one or two half-pel interpolations and one averaging operation is designed to have different execution control modes, which result in decreasing memory accesses greatly and maintaining the system efficiency. The simulation result shows that the proposed method could reduce up to 87% of power caused by data transfers over the conventional method in MC module.
AB - Power-aware design is one of the most important areas to be emphasized in multimedia mobile systems, in which data transfers dominate the power consumption. In this paper, we propose a new architecture for motion compensation (MC) of H.264/AVC with power reduction by decreasing the data transfers. For this purpose, a reconfigurable microarchitecture based on data type is proposed for interpolation and it is mapped onto the dedicated motion compensation IP (intellectual property) effectively without sacrificing the performance or the system latency, The original quarter-pel interpolation equation that consists of one or two half-pel interpolations and one averaging operation is designed to have different execution control modes, which result in decreasing memory accesses greatly and maintaining the system efficiency. The simulation result shows that the proposed method could reduce up to 87% of power caused by data transfers over the conventional method in MC module.
UR - http://www.scopus.com/inward/record.url?scp=33744902628&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=33744902628&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:33744902628
SN - 3540308814
SN - 9783540308812
VL - 3820 LNCS
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 39
EP - 49
BT - Embedded Software and Systems
ER -