Abstract
Software-managed architectures, which use scratch-pad memories (SPMs), are a promising alternative to cached-based architectures for multicores. SPMs provide scalability but require explicit management. For example, to use an instruction SPM, explicit management code needs to be inserted around every call site to load functions to the SPM. such management code would check the state of the SPM and perform loading operations if necessary, which can cause considerable overhead at runtime. In this paper, we propose a compiler-based approach to reduce this overhead by identifying management code that can be removed or simplified. Our experiments with various benchmarks show that our approach reduces the execution time by 14% on average. In addition, compared to hardware caching, using our approach on an SPM-based architecture can reduce the execution times of the benchmarks by up to 15%.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 1241-1244 |
| Number of pages | 4 |
| ISBN (Electronic) | 9783981537093 |
| DOIs | |
| Publication status | Published - 2017 May 11 |
| Event | 20th Design, Automation and Test in Europe, DATE 2017 - Swisstech, Lausanne, Switzerland Duration: 2017 Mar 27 → 2017 Mar 31 |
Publication series
| Name | Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017 |
|---|
Other
| Other | 20th Design, Automation and Test in Europe, DATE 2017 |
|---|---|
| Country | Switzerland |
| City | Swisstech, Lausanne |
| Period | 17/3/27 → 17/3/31 |
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All Science Journal Classification (ASJC) codes
- Computer Networks and Communications
- Hardware and Architecture
- Safety, Risk, Reliability and Quality
Cite this
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Reducing code management overhead in software-managed multicores. / Cai, Jian; Kim, Yooseong; Kim, Youngbin; Shrivastava, Aviral; Lee, Kyoungwoo.
Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 1241-1244 7927179 (Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Reducing code management overhead in software-managed multicores
AU - Cai, Jian
AU - Kim, Yooseong
AU - Kim, Youngbin
AU - Shrivastava, Aviral
AU - Lee, Kyoungwoo
PY - 2017/5/11
Y1 - 2017/5/11
N2 - Software-managed architectures, which use scratch-pad memories (SPMs), are a promising alternative to cached-based architectures for multicores. SPMs provide scalability but require explicit management. For example, to use an instruction SPM, explicit management code needs to be inserted around every call site to load functions to the SPM. such management code would check the state of the SPM and perform loading operations if necessary, which can cause considerable overhead at runtime. In this paper, we propose a compiler-based approach to reduce this overhead by identifying management code that can be removed or simplified. Our experiments with various benchmarks show that our approach reduces the execution time by 14% on average. In addition, compared to hardware caching, using our approach on an SPM-based architecture can reduce the execution times of the benchmarks by up to 15%.
AB - Software-managed architectures, which use scratch-pad memories (SPMs), are a promising alternative to cached-based architectures for multicores. SPMs provide scalability but require explicit management. For example, to use an instruction SPM, explicit management code needs to be inserted around every call site to load functions to the SPM. such management code would check the state of the SPM and perform loading operations if necessary, which can cause considerable overhead at runtime. In this paper, we propose a compiler-based approach to reduce this overhead by identifying management code that can be removed or simplified. Our experiments with various benchmarks show that our approach reduces the execution time by 14% on average. In addition, compared to hardware caching, using our approach on an SPM-based architecture can reduce the execution times of the benchmarks by up to 15%.
UR - http://www.scopus.com/inward/record.url?scp=85020237141&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85020237141&partnerID=8YFLogxK
U2 - 10.23919/DATE.2017.7927179
DO - 10.23919/DATE.2017.7927179
M3 - Conference contribution
T3 - Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017
SP - 1241
EP - 1244
BT - Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017
PB - Institute of Electrical and Electronics Engineers Inc.
ER -