Software-managed architectures, which use scratch-pad memories (SPMs), are a promising alternative to cached-based architectures for multicores. SPMs provide scalability but require explicit management. For example, to use an instruction SPM, explicit management code needs to be inserted around every call site to load functions to the SPM. such management code would check the state of the SPM and perform loading operations if necessary, which can cause considerable overhead at runtime. In this paper, we propose a compiler-based approach to reduce this overhead by identifying management code that can be removed or simplified. Our experiments with various benchmarks show that our approach reduces the execution time by 14% on average. In addition, compared to hardware caching, using our approach on an SPM-based architecture can reduce the execution times of the benchmarks by up to 15%.
|Title of host publication||Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||4|
|Publication status||Published - 2017 May 11|
|Event||20th Design, Automation and Test in Europe, DATE 2017 - Swisstech, Lausanne, Switzerland|
Duration: 2017 Mar 27 → 2017 Mar 31
|Name||Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017|
|Other||20th Design, Automation and Test in Europe, DATE 2017|
|Period||17/3/27 → 17/3/31|
Bibliographical notePublisher Copyright:
© 2017 IEEE.
All Science Journal Classification (ASJC) codes
- Computer Networks and Communications
- Hardware and Architecture
- Safety, Risk, Reliability and Quality