Reducing test point area for BIST through greater use of functional flip-flops to drive control points

Joon Sung Yang, Benoit Nadeau-Dostie, Nur A. Touba

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

Recently, a new test point insertion method for pseudo-random built-in self-test (BIST) was proposed in [Yang 09] which tries to use functional flip-flops to drive control test points instead of adding extra dedicated flip-flops for driving the control points. This paper investigates methods to further reduce the area overhead by replacing dedicated flip-flops which could not be replaced in [Yang 09]. A new algorithm (alternative selection algorithm) is proposed to find candidate flip-flops out of the fan-in cone of a test point. Experimental results indicate that most of the not-replaced flip-flops in [Yang 09] can be replaced and hence even more significant area reduction can be achieved with minimizing the loss of testability.

Original languageEnglish
Title of host publication2009 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2009
Pages20-28
Number of pages9
DOIs
Publication statusPublished - 2009
Event2009 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2009 - Chicago, IL, United States
Duration: 2009 Oct 72009 Oct 9

Publication series

NameProceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
ISSN (Print)1550-5774

Conference

Conference2009 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2009
CountryUnited States
CityChicago, IL
Period09/10/709/10/9

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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