Abstract
As technology scales down, the sensing margin of spin-transfer-torque random access memory is significantly degraded because of the increased process variation and decreased supply voltage. The sensing current, which is limited to prevent read disturbance, further degrades the sensing margin. To improve the sensing margin, various reference schemes have been proposed. However, it is essential to be selective because the read stability, write ability, and array efficiency are very different according to the reference schemes. This paper presents the study of a variety of reference schemes and outlines five requirements for an optimized reference scheme as follows: 1) no parasitic mismatch, 2) no regularity problem, 3) no read disturbance, 4) no write-current degradation, and 5) small area overhead. A novel reference scheme that satisfies all the requirements for the optimized reference scheme is proposed using four 1T1MTJ cells and a reference word line structure with the same parasitic scheme.
| Original language | English |
|---|---|
| Article number | 6853380 |
| Pages (from-to) | 3376-3385 |
| Number of pages | 10 |
| Journal | IEEE Transactions on Circuits and Systems I: Regular Papers |
| Volume | 61 |
| Issue number | 12 |
| DOIs | |
| Publication status | Published - 2014 Jan 1 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
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Reference-scheme study and novel reference scheme for deep submicrometer STT-RAM. / Na, Taehui; Kim, Jisu; Kim, Jung Pill; Kang, Seung H.; Jung, Seongook.
In: IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 61, No. 12, 6853380, 01.01.2014, p. 3376-3385.Research output: Contribution to journal › Article
TY - JOUR
T1 - Reference-scheme study and novel reference scheme for deep submicrometer STT-RAM
AU - Na, Taehui
AU - Kim, Jisu
AU - Kim, Jung Pill
AU - Kang, Seung H.
AU - Jung, Seongook
PY - 2014/1/1
Y1 - 2014/1/1
N2 - As technology scales down, the sensing margin of spin-transfer-torque random access memory is significantly degraded because of the increased process variation and decreased supply voltage. The sensing current, which is limited to prevent read disturbance, further degrades the sensing margin. To improve the sensing margin, various reference schemes have been proposed. However, it is essential to be selective because the read stability, write ability, and array efficiency are very different according to the reference schemes. This paper presents the study of a variety of reference schemes and outlines five requirements for an optimized reference scheme as follows: 1) no parasitic mismatch, 2) no regularity problem, 3) no read disturbance, 4) no write-current degradation, and 5) small area overhead. A novel reference scheme that satisfies all the requirements for the optimized reference scheme is proposed using four 1T1MTJ cells and a reference word line structure with the same parasitic scheme.
AB - As technology scales down, the sensing margin of spin-transfer-torque random access memory is significantly degraded because of the increased process variation and decreased supply voltage. The sensing current, which is limited to prevent read disturbance, further degrades the sensing margin. To improve the sensing margin, various reference schemes have been proposed. However, it is essential to be selective because the read stability, write ability, and array efficiency are very different according to the reference schemes. This paper presents the study of a variety of reference schemes and outlines five requirements for an optimized reference scheme as follows: 1) no parasitic mismatch, 2) no regularity problem, 3) no read disturbance, 4) no write-current degradation, and 5) small area overhead. A novel reference scheme that satisfies all the requirements for the optimized reference scheme is proposed using four 1T1MTJ cells and a reference word line structure with the same parasitic scheme.
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U2 - 10.1109/TCSI.2014.2327337
DO - 10.1109/TCSI.2014.2327337
M3 - Article
VL - 61
SP - 3376
EP - 3385
JO - IEEE Transactions on Circuits and Systems II: Express Briefs
JF - IEEE Transactions on Circuits and Systems II: Express Briefs
SN - 1549-8328
IS - 12
M1 - 6853380
ER -