Relaxation of strained Si 1-x Ge x by dry oxidation

B. G. Min, Dae Hong Ko, Mann-Ho Cho, T. W. Lee, K. J. Choi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We investigated strain changes in Si 1-x Ge x layers on silicon substrates upon oxidation. We grew Si 1-x Ge x layers with different Ge fractions (x = 0.15 and 0.3) on chemically cleaned silicon substrates by the UHV CVD process. Oxidation in a vertical furnace at 800 °C and 900 °C in an O 2 gas ambient produced a silicon oxide layer and a silicon germanium layer that was richer in Ge-content than initial Si 1-x Ge x films. Initial compressively strained Si 1-x Ge x films are fully strained in this range of Ge fractions. The strain in the Ge-rich layer increased and then decreased as the oxidation temperature and time increased. In comparison, the strain of the remaining initial Si 1-x Ge x gradually relaxed with an increase in oxidation time and temperature. The relaxation occurred through the generation of dislocations and defects at the interface of the Si (100) substrate.

Original languageEnglish
Title of host publicationECS Transactions - International Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS
Subtitle of host publicationNew Materials, Processes and Equipment, 3
Pages41-52
Number of pages12
Edition1
DOIs
Publication statusPublished - 2007 Dec 1
EventInternational Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment, 3 - 211th ECS Meeting - Chicago, IL, United States
Duration: 2007 May 62007 May 10

Publication series

NameECS Transactions
Number1
Volume6
ISSN (Print)1938-5862
ISSN (Electronic)1938-6737

Other

OtherInternational Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment, 3 - 211th ECS Meeting
CountryUnited States
CityChicago, IL
Period07/5/607/5/10

Fingerprint

Oxidation
Silicon
Substrates
Silicon oxides
Germanium
Chemical vapor deposition
Furnaces
Temperature
Defects
Gases

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Min, B. G., Ko, D. H., Cho, M-H., Lee, T. W., & Choi, K. J. (2007). Relaxation of strained Si 1-x Ge x by dry oxidation In ECS Transactions - International Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment, 3 (1 ed., pp. 41-52). (ECS Transactions; Vol. 6, No. 1). https://doi.org/10.1149/1.2727386
Min, B. G. ; Ko, Dae Hong ; Cho, Mann-Ho ; Lee, T. W. ; Choi, K. J. / Relaxation of strained Si 1-x Ge x by dry oxidation ECS Transactions - International Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment, 3. 1. ed. 2007. pp. 41-52 (ECS Transactions; 1).
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Min, BG, Ko, DH, Cho, M-H, Lee, TW & Choi, KJ 2007, Relaxation of strained Si 1-x Ge x by dry oxidation in ECS Transactions - International Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment, 3. 1 edn, ECS Transactions, no. 1, vol. 6, pp. 41-52, International Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment, 3 - 211th ECS Meeting, Chicago, IL, United States, 07/5/6. https://doi.org/10.1149/1.2727386

Relaxation of strained Si 1-x Ge x by dry oxidation . / Min, B. G.; Ko, Dae Hong; Cho, Mann-Ho; Lee, T. W.; Choi, K. J.

ECS Transactions - International Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment, 3. 1. ed. 2007. p. 41-52 (ECS Transactions; Vol. 6, No. 1).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Min BG, Ko DH, Cho M-H, Lee TW, Choi KJ. Relaxation of strained Si 1-x Ge x by dry oxidation In ECS Transactions - International Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment, 3. 1 ed. 2007. p. 41-52. (ECS Transactions; 1). https://doi.org/10.1149/1.2727386