Three-dimensional DRAM stacking has emerged as a vehicle for scaling system densities and performance improvement. The two design choices for interfacing to processors are - i) a separate core die connected to the DRAM stack via a silicon interposer (2.5D), and ii) DRAM die stacked on top of the core die (3D). These alternatives have different performance, power, and reliability behaviors. Specifically, 3D designs realize higher performance but operate at higher temperatures and thus exhibit lower lifetime. On the other hand, 2.5D designs provide lower bandwidth between the core die and the DRAM stack, but exhibit significantly longer lifetime due to less thermally-induced degradation. This paper explores this tradeoff between reliability and performance of 3D and 2.5D stacked memory systems. Our results indicate that, in general, lower voltage and frequency operations with 3D stacked systems may achieve balanced reliability-performance tradeoff.
|Title of host publication||2016 International Reliability Physics Symposium, IRPS 2016|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Publication status||Published - 2016 Sep 22|
|Event||2016 International Reliability Physics Symposium, IRPS 2016 - Pasadena, United States|
Duration: 2016 Apr 17 → 2016 Apr 21
|Name||IEEE International Reliability Physics Symposium Proceedings|
|Other||2016 International Reliability Physics Symposium, IRPS 2016|
|Period||16/4/17 → 16/4/21|
Bibliographical noteFunding Information:
This research was supported in part by the National Science Foundation under grant CNS 0855110, Sandia National Laboratories, and the Defense Advanced Research Projects Agency (DARPA) contract HR0011-14-1-0002. We also acknowledge the detailed and constructive comments of the reviewers
© 2016 IEEE.
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