Abstract
Three-dimensional DRAM stacking has emerged as a vehicle for scaling system densities and performance improvement. The two design choices for interfacing to processors are - i) a separate core die connected to the DRAM stack via a silicon interposer (2.5D), and ii) DRAM die stacked on top of the core die (3D). These alternatives have different performance, power, and reliability behaviors. Specifically, 3D designs realize higher performance but operate at higher temperatures and thus exhibit lower lifetime. On the other hand, 2.5D designs provide lower bandwidth between the core die and the DRAM stack, but exhibit significantly longer lifetime due to less thermally-induced degradation. This paper explores this tradeoff between reliability and performance of 3D and 2.5D stacked memory systems. Our results indicate that, in general, lower voltage and frequency operations with 3D stacked systems may achieve balanced reliability-performance tradeoff.
| Original language | English |
|---|---|
| Title of host publication | 2016 International Reliability Physics Symposium, IRPS 2016 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | MY21-MY25 |
| ISBN (Electronic) | 9781467391368 |
| DOIs | |
| Publication status | Published - 2016 Sep 22 |
| Event | 2016 International Reliability Physics Symposium, IRPS 2016 - Pasadena, United States Duration: 2016 Apr 17 → 2016 Apr 21 |
Publication series
| Name | IEEE International Reliability Physics Symposium Proceedings |
|---|---|
| Volume | 2016-September |
| ISSN (Print) | 1541-7026 |
Other
| Other | 2016 International Reliability Physics Symposium, IRPS 2016 |
|---|---|
| Country | United States |
| City | Pasadena |
| Period | 16/4/17 → 16/4/21 |
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All Science Journal Classification (ASJC) codes
- Engineering(all)
Cite this
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Reliability-performance tradeoffs between 2.5D and 3D-stacked DRAM processors. / Hassan, Syed Minhaj; Song, William Jinho; Mukhopadhyay, Saibal; Yalamanchili, Sudhakar.
2016 International Reliability Physics Symposium, IRPS 2016. Institute of Electrical and Electronics Engineers Inc., 2016. p. MY21-MY25 7574618 (IEEE International Reliability Physics Symposium Proceedings; Vol. 2016-September).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Reliability-performance tradeoffs between 2.5D and 3D-stacked DRAM processors
AU - Hassan, Syed Minhaj
AU - Song, William Jinho
AU - Mukhopadhyay, Saibal
AU - Yalamanchili, Sudhakar
PY - 2016/9/22
Y1 - 2016/9/22
N2 - Three-dimensional DRAM stacking has emerged as a vehicle for scaling system densities and performance improvement. The two design choices for interfacing to processors are - i) a separate core die connected to the DRAM stack via a silicon interposer (2.5D), and ii) DRAM die stacked on top of the core die (3D). These alternatives have different performance, power, and reliability behaviors. Specifically, 3D designs realize higher performance but operate at higher temperatures and thus exhibit lower lifetime. On the other hand, 2.5D designs provide lower bandwidth between the core die and the DRAM stack, but exhibit significantly longer lifetime due to less thermally-induced degradation. This paper explores this tradeoff between reliability and performance of 3D and 2.5D stacked memory systems. Our results indicate that, in general, lower voltage and frequency operations with 3D stacked systems may achieve balanced reliability-performance tradeoff.
AB - Three-dimensional DRAM stacking has emerged as a vehicle for scaling system densities and performance improvement. The two design choices for interfacing to processors are - i) a separate core die connected to the DRAM stack via a silicon interposer (2.5D), and ii) DRAM die stacked on top of the core die (3D). These alternatives have different performance, power, and reliability behaviors. Specifically, 3D designs realize higher performance but operate at higher temperatures and thus exhibit lower lifetime. On the other hand, 2.5D designs provide lower bandwidth between the core die and the DRAM stack, but exhibit significantly longer lifetime due to less thermally-induced degradation. This paper explores this tradeoff between reliability and performance of 3D and 2.5D stacked memory systems. Our results indicate that, in general, lower voltage and frequency operations with 3D stacked systems may achieve balanced reliability-performance tradeoff.
UR - http://www.scopus.com/inward/record.url?scp=84990963220&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84990963220&partnerID=8YFLogxK
U2 - 10.1109/IRPS.2016.7574618
DO - 10.1109/IRPS.2016.7574618
M3 - Conference contribution
T3 - IEEE International Reliability Physics Symposium Proceedings
SP - MY21-MY25
BT - 2016 International Reliability Physics Symposium, IRPS 2016
PB - Institute of Electrical and Electronics Engineers Inc.
ER -