Abstract
Physical Unclonable Functions (PUFs) can be utilized for secret key generation in security applications. Since the inherent randomness of PUF can degrade its reliability, most of the existing PUF architectures have designed post-processing logic to enhance the reliability such as an error correction function for guaranteeing reliability. However, the structures incur high cost in terms of implementation area and power consumption. This paper introduces a Various Index Voting Architecture (VIVA) that can enhance the reliability with a low overhead compared to the conventional schemes. The proposed architecture is based on an index-based scheme with simple computation logic units and iterative operations to generate multiple indices for the accuracy of key generation. Our evaluation results show that the proposed architecture reduces the hardware implementation overhead by 2 to more than 5 times, without losing a key generation failure probability compared to conventional approaches.
Original language | English |
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Title of host publication | Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020 |
Editors | Giorgio Di Natale, Cristiana Bolchini, Elena-Ioana Vatajelu |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 352-357 |
Number of pages | 6 |
ISBN (Electronic) | 9783981926347 |
DOIs | |
Publication status | Published - 2020 Mar |
Event | 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020 - Grenoble, France Duration: 2020 Mar 9 → 2020 Mar 13 |
Publication series
Name | Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020 |
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Conference
Conference | 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020 |
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Country/Territory | France |
City | Grenoble |
Period | 20/3/9 → 20/3/13 |
Bibliographical note
Funding Information:ACKNOWLEDGMENT This work was supported by Samsung Research Funding Center of Samsung Electronics under Project Number SRFC-TB1803-02.
Publisher Copyright:
© 2020 EDAA.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Safety, Risk, Reliability and Quality
- Modelling and Simulation
- Electrical and Electronic Engineering