Research on a high-performance processor with branch instruction history length control

Two-level branch predictors are integrated in most modern processors. The predictor estimates an outcome of branch instruction using both a table of state counters and a register of recently executed branch outcomes. However, among the recently executed branch outcomes, some are useful while others are useless information and might prevent accurate prediction. Therefore, this useless information needs to be changed to improve branch prediction. In this paper, we presents program counter added history length adjustment (PCaHLA) branch predictor that utilizes a branch instruction's program counter bits instead of resetting the branch history register's (BHR) unnecessary bits to 0 while executing exclusive-or arithmetic using the branch instruction's program counter value to predict branch instruction. The PCaHLA branch predictor increases pattern history table (PHT) utilization and decreases the Aliasing occurrence ratio to increase prediction accuracy. Compared with the Gshare branch predictor, one of the most popular two-level branch predictors, the suggested structure increases accuracy by 0.9% on average. There is also a 2.03% performance gain on average in using the branch instruction's program counter value instead of resetting unnecessary branch history register bits to 0.