A small area, low power CMOS four-quadrant multiplier is proposed. It is based on a Linear Differential Amplifier(LDA), a multiplier core and a fully differential folded cascode(FC) output stage. The conventional resistor load implementation is avoided by converting a fully differential output current of the multiplier core into a fully differential voltage signal by a folded cascode transresistance amplifier. This configuration not only improves the linearity but also occupies small area. The test CMOS-chip is functional and only consumes 360μW for a ±3V power supply. The total silicon area is only 0.07mm2. The input voltage range is a function of the bias current. Experimental results show less than 1% linearity error for ±1V input.
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|Publication status||Published - 1996 Jan 1|
|Event||Proceedings of the 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4) - Atlanta, GA, USA|
Duration: 1996 May 12 → 1996 May 15
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering