Edge detection is one of the key stages of image processing and feature extraction. The Canny edge detector is the most popular edge detector because of its ability to detect edges in noisy images. However, it is a time and resource consuming algorithm which contain many stages. So we need to reduce the size of the Canny edge detector. In this paper, a hardware architecture for Canny edge detector is proposed. A 5 by 5 sliding window is adopted to conduct image smoothing and get gradient at the same time. By using same divider value twice, the angular value for all edges with one degree resolution is obtained. Synthesis and simulation results are presented.
|Title of host publication||ISOCC 2016 - International SoC Design Conference|
|Subtitle of host publication||Smart SoC for Intelligent Things|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||2|
|Publication status||Published - 2016 Dec 27|
|Event||13th International SoC Design Conference, ISOCC 2016 - Jeju, Korea, Republic of|
Duration: 2016 Oct 23 → 2016 Oct 26
|Name||ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things|
|Other||13th International SoC Design Conference, ISOCC 2016|
|Country/Territory||Korea, Republic of|
|Period||16/10/23 → 16/10/26|
Bibliographical noteFunding Information:
This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korean government (MSIP) (No. NRF-2015R1A2A2A01004883), and was also supported by IDEC(IPC, EDA Tool, MPW).
© 2016 IEEE.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering