Resource-efficient FPGA architecture of canny edge detector

Yunseok Jang, Junwon Mun, Jaeseok Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

Edge detection is one of the key stages of image processing and feature extraction. The Canny edge detector is the most popular edge detector because of its ability to detect edges in noisy images. However, it is a time and resource consuming algorithm which contain many stages. So we need to reduce the size of the Canny edge detector. In this paper, a hardware architecture for Canny edge detector is proposed. A 5 by 5 sliding window is adopted to conduct image smoothing and get gradient at the same time. By using same divider value twice, the angular value for all edges with one degree resolution is obtained. Synthesis and simulation results are presented.

Original languageEnglish
Title of host publicationISOCC 2016 - International SoC Design Conference
Subtitle of host publicationSmart SoC for Intelligent Things
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages299-300
Number of pages2
ISBN (Electronic)9781467393089
DOIs
Publication statusPublished - 2016 Dec 27
Event13th International SoC Design Conference, ISOCC 2016 - Jeju, Korea, Republic of
Duration: 2016 Oct 232016 Oct 26

Publication series

NameISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things

Other

Other13th International SoC Design Conference, ISOCC 2016
CountryKorea, Republic of
CityJeju
Period16/10/2316/10/26

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Instrumentation

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  • Cite this

    Jang, Y., Mun, J., & Kim, J. (2016). Resource-efficient FPGA architecture of canny edge detector. In ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things (pp. 299-300). [7799796] (ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2016.7799796