In LTE(Long-Term Evolution) system, UE(User Equipment) performs synchronization processing with a specific cell to communicate. In that processing, the UE uses a matched filter to filter PSS(Primary Synchronization Signal) from downlink signals sent from the cell. There are various ways to design such a matched filter. In the most native design of the matched filter, the number of multipliers is required as much as a number of the taps which means filter length. If resources are limited, that is a very inefficient design approach. Therefore, we proposed filter design method to significantly reduce the number of multipliers in the matched filter by utilizing the difference of between sampling rate and operating clock frequency. When using FPGA resources for designing the filter, The filter design method proposed in this paper reduced the LUT(look-up table) utilization by 55.2% to 6.22%, the FF(flip-flop) utilization decreased by 24.95% to 4.44%, and the BRAM utilization decreased by 42.65% to 13.05% than the Natively design method.
|Title of host publication||Proceedings - International SoC Design Conference, ISOCC 2020|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||2|
|Publication status||Published - 2020 Oct 21|
|Event||17th International System-on-Chip Design Conference, ISOCC 2020 - Yeosu, Korea, Republic of|
Duration: 2020 Oct 21 → 2020 Oct 24
|Name||Proceedings - International SoC Design Conference, ISOCC 2020|
|Conference||17th International System-on-Chip Design Conference, ISOCC 2020|
|Country/Territory||Korea, Republic of|
|Period||20/10/21 → 20/10/24|
Bibliographical noteFunding Information:
ACKNOWLEDGMENT This research was supported by R&D program for advanced integrated-intelligence for identification through the National Research Foundation of Korea(NRF) funded by Ministry of Trade, Industry and Energy (2018M3E3A1057248), And the chip fabrication and EDA Tool were supported by the IC Design Education Center.
© 2020 IEEE.
All Science Journal Classification (ASJC) codes
- Energy Engineering and Power Technology
- Electrical and Electronic Engineering
- Artificial Intelligence
- Hardware and Architecture