This paper presents a Via programmable read only memory (Via-ROM) for Vmin and macro-yield enhancement through robust ROM designs based on 45nm process. The main stability issues in ROM are 1) lower on-cell (NMOS) current, 2) higher keeper (PMOS) current, and 3) higher bit-line (BL) parasitic value. To improve the Vmin and macro-yield, the robust ROM design schemes are implemented as follows. 1) ROM bit cell size optimization without increasing a bit cell area, 2) BL loading reduction to use a rom code pattern optimization, 3) selective full BL pre-charge and keeper control to use an external pin named as KCS (Keeper Control Signal) and 4) wide pulse width generator using an asynchronous 3-bit ripple binary counter. These schemes to improve 0 read margin were confirmed by both the simulation and the measurement. Experimental results show that macro-yield improved from 0% to 100% at 1.1V (Voperation) and -40°C.
|Title of host publication||2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||4|
|Publication status||Published - 2015 Jul 27|
|Event||IEEE International Symposium on Circuits and Systems, ISCAS 2015 - Lisbon, Portugal|
Duration: 2015 May 24 → 2015 May 27
|Name||Proceedings - IEEE International Symposium on Circuits and Systems|
|Conference||IEEE International Symposium on Circuits and Systems, ISCAS 2015|
|Period||15/5/24 → 15/5/27|
Bibliographical notePublisher Copyright:
© 2015 IEEE.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering