Robust via-programmable ROM design based on 45nm process considering process variation and enhancement Vmin and yield

Byung Jun Jang, Chan Ho Lee, Sung Hun Sim, Kyu Won Choi, Do Hun Byun, Yeon Ho Jung, Ki Man Park, Dong Yeon Heo, Gyu Hong Kim, Joon Sung Yang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper presents a Via programmable read only memory (Via-ROM) for Vmin and macro-yield enhancement through robust ROM designs based on 45nm process. The main stability issues in ROM are 1) lower on-cell (NMOS) current, 2) higher keeper (PMOS) current, and 3) higher bit-line (BL) parasitic value. To improve the Vmin and macro-yield, the robust ROM design schemes are implemented as follows. 1) ROM bit cell size optimization without increasing a bit cell area, 2) BL loading reduction to use a rom code pattern optimization, 3) selective full BL pre-charge and keeper control to use an external pin named as KCS (Keeper Control Signal) and 4) wide pulse width generator using an asynchronous 3-bit ripple binary counter. These schemes to improve 0 read margin were confirmed by both the simulation and the measurement. Experimental results show that macro-yield improved from 0% to 100% at 1.1V (Voperation) and -40°C.

Original languageEnglish
Title of host publication2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages2541-2544
Number of pages4
ISBN (Electronic)9781479983919
DOIs
Publication statusPublished - 2015 Jul 27
EventIEEE International Symposium on Circuits and Systems, ISCAS 2015 - Lisbon, Portugal
Duration: 2015 May 242015 May 27

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2015-July
ISSN (Print)0271-4310

Conference

ConferenceIEEE International Symposium on Circuits and Systems, ISCAS 2015
CountryPortugal
CityLisbon
Period15/5/2415/5/27

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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    Jang, B. J., Lee, C. H., Sim, S. H., Choi, K. W., Byun, D. H., Jung, Y. H., Park, K. M., Heo, D. Y., Kim, G. H., & Yang, J. S. (2015). Robust via-programmable ROM design based on 45nm process considering process variation and enhancement Vmin and yield. In 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015 (pp. 2541-2544). [7169203] (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2015-July). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2015.7169203