Robust via-programmable ROM design based on 45nm process considering process variation and enhancement Vmin and yield

Byung Jun Jang; Chan Ho Lee; Sung Hun Sim; Kyu Won Choi; Do Hun Byun; Yeon Ho Jung; Ki Man Park; Dong Yeon Heo; Gyu Hong Kim; Joon Sung Yang

doi:10.1109/ISCAS.2015.7169203

Robust via-programmable ROM design based on 45nm process considering process variation and enhancement V_min and yield

Byung Jun Jang, Chan Ho Lee, Sung Hun Sim, Kyu Won Choi, Do Hun Byun, Yeon Ho Jung, Ki Man Park, Dong Yeon Heo, Gyu Hong Kim, Joon Sung Yang

College of Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

This paper presents a Via programmable read only memory (Via-ROM) for V_min and macro-yield enhancement through robust ROM designs based on 45nm process. The main stability issues in ROM are 1) lower on-cell (NMOS) current, 2) higher keeper (PMOS) current, and 3) higher bit-line (BL) parasitic value. To improve the V_min and macro-yield, the robust ROM design schemes are implemented as follows. 1) ROM bit cell size optimization without increasing a bit cell area, 2) BL loading reduction to use a rom code pattern optimization, 3) selective full BL pre-charge and keeper control to use an external pin named as KCS (Keeper Control Signal) and 4) wide pulse width generator using an asynchronous 3-bit ripple binary counter. These schemes to improve 0 read margin were confirmed by both the simulation and the measurement. Experimental results show that macro-yield improved from 0% to 100% at 1.1V (V_operation) and -40°C.

Original language	English
Title of host publication	2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	2541-2544
Number of pages	4
ISBN (Electronic)	9781479983919
DOIs	https://doi.org/10.1109/ISCAS.2015.7169203
Publication status	Published - 2015 Jul 27
Event	IEEE International Symposium on Circuits and Systems, ISCAS 2015 - Lisbon, Portugal Duration: 2015 May 24 → 2015 May 27

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2015-July
ISSN (Print)	0271-4310

Conference

Conference	IEEE International Symposium on Circuits and Systems, ISCAS 2015
Country/Territory	Portugal
City	Lisbon
Period	15/5/24 → 15/5/27

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2015.7169203

Cite this

Jang, B. J., Lee, C. H., Sim, S. H., Choi, K. W., Byun, D. H., Jung, Y. H., Park, K. M., Heo, D. Y., Kim, G. H., & Yang, J. S. (2015). Robust via-programmable ROM design based on 45nm process considering process variation and enhancement V_min and yield. In 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015 (pp. 2541-2544). [7169203] (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2015-July). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2015.7169203

Jang, Byung Jun ; Lee, Chan Ho ; Sim, Sung Hun et al. / Robust via-programmable ROM design based on 45nm process considering process variation and enhancement V_min and yield. 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 2541-2544 (Proceedings - IEEE International Symposium on Circuits and Systems).

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title = "Robust via-programmable ROM design based on 45nm process considering process variation and enhancement Vmin and yield",

abstract = "This paper presents a Via programmable read only memory (Via-ROM) for Vmin and macro-yield enhancement through robust ROM designs based on 45nm process. The main stability issues in ROM are 1) lower on-cell (NMOS) current, 2) higher keeper (PMOS) current, and 3) higher bit-line (BL) parasitic value. To improve the Vmin and macro-yield, the robust ROM design schemes are implemented as follows. 1) ROM bit cell size optimization without increasing a bit cell area, 2) BL loading reduction to use a rom code pattern optimization, 3) selective full BL pre-charge and keeper control to use an external pin named as KCS (Keeper Control Signal) and 4) wide pulse width generator using an asynchronous 3-bit ripple binary counter. These schemes to improve 0 read margin were confirmed by both the simulation and the measurement. Experimental results show that macro-yield improved from 0% to 100% at 1.1V (Voperation) and -40°C.",

author = "Jang, {Byung Jun} and Lee, {Chan Ho} and Sim, {Sung Hun} and Choi, {Kyu Won} and Byun, {Do Hun} and Jung, {Yeon Ho} and Park, {Ki Man} and Heo, {Dong Yeon} and Kim, {Gyu Hong} and Yang, {Joon Sung}",

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year = "2015",

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doi = "10.1109/ISCAS.2015.7169203",

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Jang, BJ, Lee, CH, Sim, SH, Choi, KW, Byun, DH, Jung, YH, Park, KM, Heo, DY, Kim, GH & Yang, JS 2015, Robust via-programmable ROM design based on 45nm process considering process variation and enhancement V_min and yield. in 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015., 7169203, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2015-July, Institute of Electrical and Electronics Engineers Inc., pp. 2541-2544, IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, 15/5/24. https://doi.org/10.1109/ISCAS.2015.7169203

Robust via-programmable ROM design based on 45nm process considering process variation and enhancement V_min and yield. / Jang, Byung Jun; Lee, Chan Ho; Sim, Sung Hun et al.

2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 2541-2544 7169203 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2015-July).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Jang, Byung Jun

AU - Lee, Chan Ho

AU - Sim, Sung Hun

AU - Choi, Kyu Won

AU - Byun, Do Hun

AU - Jung, Yeon Ho

AU - Park, Ki Man

AU - Heo, Dong Yeon

AU - Kim, Gyu Hong

AU - Yang, Joon Sung

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N2 - This paper presents a Via programmable read only memory (Via-ROM) for Vmin and macro-yield enhancement through robust ROM designs based on 45nm process. The main stability issues in ROM are 1) lower on-cell (NMOS) current, 2) higher keeper (PMOS) current, and 3) higher bit-line (BL) parasitic value. To improve the Vmin and macro-yield, the robust ROM design schemes are implemented as follows. 1) ROM bit cell size optimization without increasing a bit cell area, 2) BL loading reduction to use a rom code pattern optimization, 3) selective full BL pre-charge and keeper control to use an external pin named as KCS (Keeper Control Signal) and 4) wide pulse width generator using an asynchronous 3-bit ripple binary counter. These schemes to improve 0 read margin were confirmed by both the simulation and the measurement. Experimental results show that macro-yield improved from 0% to 100% at 1.1V (Voperation) and -40°C.

AB - This paper presents a Via programmable read only memory (Via-ROM) for Vmin and macro-yield enhancement through robust ROM designs based on 45nm process. The main stability issues in ROM are 1) lower on-cell (NMOS) current, 2) higher keeper (PMOS) current, and 3) higher bit-line (BL) parasitic value. To improve the Vmin and macro-yield, the robust ROM design schemes are implemented as follows. 1) ROM bit cell size optimization without increasing a bit cell area, 2) BL loading reduction to use a rom code pattern optimization, 3) selective full BL pre-charge and keeper control to use an external pin named as KCS (Keeper Control Signal) and 4) wide pulse width generator using an asynchronous 3-bit ripple binary counter. These schemes to improve 0 read margin were confirmed by both the simulation and the measurement. Experimental results show that macro-yield improved from 0% to 100% at 1.1V (Voperation) and -40°C.

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BT - 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015

PB - Institute of Electrical and Electronics Engineers Inc.

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Jang BJ, Lee CH, Sim SH, Choi KW, Byun DH, Jung YH et al. Robust via-programmable ROM design based on 45nm process considering process variation and enhancement V_min and yield. In 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 2541-2544. 7169203. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: 10.1109/ISCAS.2015.7169203