Sampling based design verification using design error models

Research output: Contribution to journalConference article

Abstract

A new simulation based design verification system employing design error models and statistical sampling techniques, is developed. It provides a simulation coverage which can be used as a guide in the verification process, and estimates the coverage quickly using sampling techniques. The simulation results demonstrate the effectiveness of this approach. This system can be used as an efficient design verification tool to reduce the overall design cycle time.

Original languageEnglish
Pages (from-to)197-200
Number of pages4
JournalProceedings of the Annual IEEE International ASIC Conference and Exhibit
Publication statusPublished - 1996 Jan 1

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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