Recent advances in flash technologies, such as scaling and multi-leveling schemes, have been successful to make flash denser and secure more storage spaces per die. Unfortunately, these technology advances significantly degrade flash’s reliability due to a smaller cell geometry and a finer-grained cell state control. In this paper, we propose a state-aware reliability optimization technique (SARO), new flash optimization that improves the flash reliability under diverse scaling and multi-leveling schemes. To this end, we first reveal that reliability-related flash errors are highly skewed among flash cell States, which was not captured by prior studies. The proposed SARO exploits then the different per-state error behavior in flash cell States by selecting the most error-prone flash States (for each error type) and by forming narrow threshold voltage distributions (for the selected States only). Furthermore, SARO is applied only when the program time gets shorter because of flash cell aging, thereby keeping the program latency unchanged. Our experimental results with real MLC and TLC flash devices show that SARO can reduce a significant number of flash bit errors, which can in turn reduce the read latency by 40%, on average.
|Title of host publication||GLSVLSI 2018 - Proceedings of the 2018 Great Lakes Symposium on VLSI|
|Publisher||Association for Computing Machinery|
|Number of pages||6|
|Publication status||Published - 2018 May 30|
|Event||28th Great Lakes Symposium on VLSI, GLSVLSI 2018 - Chicago, United States|
Duration: 2018 May 23 → 2018 May 25
|Name||Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI|
|Other||28th Great Lakes Symposium on VLSI, GLSVLSI 2018|
|Period||18/5/23 → 18/5/25|
Bibliographical noteFunding Information:
This work was supported by Samsung Research Funding & Incubation Center of Samsung Electronics under Project Number SRFC-IT1701-11.
© 2018 Association for Computing Machinery.
All Science Journal Classification (ASJC) codes