NVMe is designed to unshackle flash from a traditional storage bus by allowing hosts to employ many threads to achieve higher bandwidth. While NVMe enables users to fully exploit all levels of parallelism offered by modern SSDs, current firmware designs are not scalable and have difficulty in handling a large number of I/O requests in parallel due to its limited computation power and many hardware contentions. We propose DeepFlash, a novel manycore-based storage platform that can process more than a million I/O requests in a second (1MIOPS) while hiding long latencies imposed by its internal flash media. Inspired by a parallel data analysis system, we design the firmware based on many-to-many threading model that can be scaled horizontally. The proposed DeepFlash can extract the maximum performance of the underlying flash memory complex by concurrently executing multiple firmware components across many cores within the device. To show its extreme parallel scalability, we implement DeepFlash on a many-core prototype processor that employs dozens of lightweight cores, analyze new challenges from parallel I/O processing and address the challenges by applying concurrency-aware optimizations. Our comprehensive evaluation reveals that DeepFlash can serve around 4.5 GB/s, while minimizing the CPU demand on microbenchmarks and real server workloads.
|Title of host publication||Proceedings of the 18th USENIX Conference on File and Storage Technologies, FAST 2020|
|Number of pages||16|
|Publication status||Published - 2020|
|Event||18th USENIX Conference on File and Storage Technologies, FAST 2020 - Santa Clara, United States|
Duration: 2020 Feb 25 → 2020 Feb 27
|Name||Proceedings of the 18th USENIX Conference on File and Storage Technologies, FAST 2020|
|Conference||18th USENIX Conference on File and Storage Technologies, FAST 2020|
|Period||20/2/25 → 20/2/27|
Bibliographical noteFunding Information:
The authors thank Keith Smith for shepherding their paper. This research is mainly supported by NRF 2016R1C182015312, MemRay grant (G01190170) and KAIST start-up package (G01190015). J. Zhang and M. Kwon equally contribute to the work. Myoungsoo Jung is the corresponding author.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Computer Networks and Communications