Scan chain swapping using TSVs for test power reduction in 3D-IC

Ingeol Lee, Jaeseok Park, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Although the hot issue of chip design becomes 3-dimensional IC, design for testability is still mandatory part of chip design. Scan structure is widely used for system reliability. However, power consumption and heat problems are necessarily considered when design is under test. In this paper, scan chain swapping method using TSVs is presented to reduce shift power in scan in operation. Proper X-filling and swapping algorithm can improve proposed scan chain swapping method. The experiment result demonstrates the power reduction in test mode.

Original languageEnglish
Title of host publicationISOCC 2013 - 2013 International SoC Design Conference
PublisherIEEE Computer Society
Pages170-171
Number of pages2
ISBN (Print)9781479911417
DOIs
Publication statusPublished - 2013 Jan 1
Event2013 International SoC Design Conference, ISOCC 2013 - Busan, Korea, Republic of
Duration: 2013 Nov 172013 Nov 19

Other

Other2013 International SoC Design Conference, ISOCC 2013
CountryKorea, Republic of
CityBusan
Period13/11/1713/11/19

Fingerprint

Design for testability
Heat problems
Electric power utilization
Experiments
Integrated circuit design

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Lee, I., Park, J., & Kang, S. (2013). Scan chain swapping using TSVs for test power reduction in 3D-IC. In ISOCC 2013 - 2013 International SoC Design Conference (pp. 170-171). [6863963] IEEE Computer Society. https://doi.org/10.1109/ISOCC.2013.6863963
Lee, Ingeol ; Park, Jaeseok ; Kang, Sungho. / Scan chain swapping using TSVs for test power reduction in 3D-IC. ISOCC 2013 - 2013 International SoC Design Conference. IEEE Computer Society, 2013. pp. 170-171
@inproceedings{807f29d524804fcdb0122ffa644e83ab,
title = "Scan chain swapping using TSVs for test power reduction in 3D-IC",
abstract = "Although the hot issue of chip design becomes 3-dimensional IC, design for testability is still mandatory part of chip design. Scan structure is widely used for system reliability. However, power consumption and heat problems are necessarily considered when design is under test. In this paper, scan chain swapping method using TSVs is presented to reduce shift power in scan in operation. Proper X-filling and swapping algorithm can improve proposed scan chain swapping method. The experiment result demonstrates the power reduction in test mode.",
author = "Ingeol Lee and Jaeseok Park and Sungho Kang",
year = "2013",
month = "1",
day = "1",
doi = "10.1109/ISOCC.2013.6863963",
language = "English",
isbn = "9781479911417",
pages = "170--171",
booktitle = "ISOCC 2013 - 2013 International SoC Design Conference",
publisher = "IEEE Computer Society",
address = "United States",

}

Lee, I, Park, J & Kang, S 2013, Scan chain swapping using TSVs for test power reduction in 3D-IC. in ISOCC 2013 - 2013 International SoC Design Conference., 6863963, IEEE Computer Society, pp. 170-171, 2013 International SoC Design Conference, ISOCC 2013, Busan, Korea, Republic of, 13/11/17. https://doi.org/10.1109/ISOCC.2013.6863963

Scan chain swapping using TSVs for test power reduction in 3D-IC. / Lee, Ingeol; Park, Jaeseok; Kang, Sungho.

ISOCC 2013 - 2013 International SoC Design Conference. IEEE Computer Society, 2013. p. 170-171 6863963.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Scan chain swapping using TSVs for test power reduction in 3D-IC

AU - Lee, Ingeol

AU - Park, Jaeseok

AU - Kang, Sungho

PY - 2013/1/1

Y1 - 2013/1/1

N2 - Although the hot issue of chip design becomes 3-dimensional IC, design for testability is still mandatory part of chip design. Scan structure is widely used for system reliability. However, power consumption and heat problems are necessarily considered when design is under test. In this paper, scan chain swapping method using TSVs is presented to reduce shift power in scan in operation. Proper X-filling and swapping algorithm can improve proposed scan chain swapping method. The experiment result demonstrates the power reduction in test mode.

AB - Although the hot issue of chip design becomes 3-dimensional IC, design for testability is still mandatory part of chip design. Scan structure is widely used for system reliability. However, power consumption and heat problems are necessarily considered when design is under test. In this paper, scan chain swapping method using TSVs is presented to reduce shift power in scan in operation. Proper X-filling and swapping algorithm can improve proposed scan chain swapping method. The experiment result demonstrates the power reduction in test mode.

UR - http://www.scopus.com/inward/record.url?scp=84906897820&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84906897820&partnerID=8YFLogxK

U2 - 10.1109/ISOCC.2013.6863963

DO - 10.1109/ISOCC.2013.6863963

M3 - Conference contribution

SN - 9781479911417

SP - 170

EP - 171

BT - ISOCC 2013 - 2013 International SoC Design Conference

PB - IEEE Computer Society

ER -

Lee I, Park J, Kang S. Scan chain swapping using TSVs for test power reduction in 3D-IC. In ISOCC 2013 - 2013 International SoC Design Conference. IEEE Computer Society. 2013. p. 170-171. 6863963 https://doi.org/10.1109/ISOCC.2013.6863963