Scan chain swapping using TSVs for test power reduction in 3D-IC

Ingeol Lee, Jaeseok Park, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Although the hot issue of chip design becomes 3-dimensional IC, design for testability is still mandatory part of chip design. Scan structure is widely used for system reliability. However, power consumption and heat problems are necessarily considered when design is under test. In this paper, scan chain swapping method using TSVs is presented to reduce shift power in scan in operation. Proper X-filling and swapping algorithm can improve proposed scan chain swapping method. The experiment result demonstrates the power reduction in test mode.

Original languageEnglish
Title of host publicationISOCC 2013 - 2013 International SoC Design Conference
PublisherIEEE Computer Society
Pages170-171
Number of pages2
ISBN (Print)9781479911417
DOIs
Publication statusPublished - 2013 Jan 1
Event2013 International SoC Design Conference, ISOCC 2013 - Busan, Korea, Republic of
Duration: 2013 Nov 172013 Nov 19

Other

Other2013 International SoC Design Conference, ISOCC 2013
CountryKorea, Republic of
CityBusan
Period13/11/1713/11/19

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All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Lee, I., Park, J., & Kang, S. (2013). Scan chain swapping using TSVs for test power reduction in 3D-IC. In ISOCC 2013 - 2013 International SoC Design Conference (pp. 170-171). [6863963] IEEE Computer Society. https://doi.org/10.1109/ISOCC.2013.6863963