Scenario-aware bus functional modeling for architecture-level performance analysis

Eui Young Chung, Hyuk Jun Lee, Sung Woo Chung

Research output: Contribution to journalArticle

Abstract

We present a scenario-aware bus functional modeling method which improves the accuracy of traditional methods without sacrificing the simulation run time. Existing methods focused on the behavior of individual IP (Intellectual Property) components and neglected the interplay effects among them, resulting in accuracy degradation from the system perspective. On the other hand, our method thoroughly considers such effects and increases the analysis accuracy by adopting control signal modeling and hierarchical stochastic modeling. Furthermore, our method minimizes the additional design time by reusing the simulation results of each IP component and an automated design flow. The experimental results show that the accuracy of our method is over 90 of RTL simulation in a multimedia SoC (System-on-Chip) design.

Original languageEnglish
Pages (from-to)875-878
Number of pages4
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE90-A
Issue number4
DOIs
Publication statusPublished - 2007 Apr

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

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