Segmented scan architecture using segment for test cost reduction

Myung Hoon Yang, Taejin Kim, Yongjoon Kim, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

This paper presents a segmented scan architecture to both test application time and test power consumption. proposed scan architecture partitions scan chains into segments and groups these segments into several segment groups. All segments within each compatible group are filled with test vector data in parallel. Since shift operations are limited to segments, the test application and test power can be significantly reduced.

Original languageEnglish
Title of host publication2008 International SoC Design Conference, ISOCC 2008
DOIs
Publication statusPublished - 2008 Dec 1
Event2008 International SoC Design Conference, ISOCC 2008 - Busan, Korea, Republic of
Duration: 2008 Nov 242008 Nov 25

Publication series

Name2008 International SoC Design Conference, ISOCC 2008
Volume1

Other

Other2008 International SoC Design Conference, ISOCC 2008
CountryKorea, Republic of
CityBusan
Period08/11/2408/11/25

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All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Software

Cite this

Yang, M. H., Kim, T., Kim, Y., & Kang, S. (2008). Segmented scan architecture using segment for test cost reduction. In 2008 International SoC Design Conference, ISOCC 2008 [4815651] (2008 International SoC Design Conference, ISOCC 2008; Vol. 1). https://doi.org/10.1109/SOCDC.2008.4815651