Abstract
Coarse-Grained Reconfigurable Architectures or CGRAs are drawing significant attention since they promise both performance with parallelism and flexibility with reconfiguration. Soft errors or transient faults are becoming a serious design concern in embedded systems including CGRAs since soft error rate is increasing exponentially as technology scaling. A recently proposed software-based technique with TMR (Triple Modular Redundancy) implemented on CGRAs incurs extreme performance overhead mainly due to expensive voting mechanisms for outputs from triplication of every operation. In this paper, we propose selective validation mechanisms for efficient modular redundancy techniques in the datapaths on CGRAs. Our techniques selectively validate results at synchronous operations rather than every operation in order to reduce the expensive performance overhead from the validation mechanism. Our experimental results demonstrate that our selective validation based TMR technique can improve the performance by 38.3% on average over benchmarks as compared to the recently proposed software-based TMR technique with the full validation.
| Original language | English |
|---|---|
| Title of host publication | ASAP 2013 - Proceedings of the 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors |
| Pages | 95-98 |
| Number of pages | 4 |
| DOIs | |
| Publication status | Published - 2013 Sep 9 |
| Event | 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2013 - Washington, DC, United States Duration: 2013 Jun 5 → 2013 Jun 7 |
Publication series
| Name | Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors |
|---|---|
| ISSN (Print) | 1063-6862 |
Other
| Other | 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2013 |
|---|---|
| Country | United States |
| City | Washington, DC |
| Period | 13/6/5 → 13/6/7 |
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All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Computer Networks and Communications
Cite this
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Selective validations for efficient protections on Coarse-Grained Reconfigurable Architectures. / Kang, Jihoon; Ko, Yohan; Lee, Jongwon; Kim, Yongjoo; So, Hwisoo; Lee, Kyoungwoo; Paek, Yunheung.
ASAP 2013 - Proceedings of the 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors. 2013. p. 95-98 6567558 (Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Selective validations for efficient protections on Coarse-Grained Reconfigurable Architectures
AU - Kang, Jihoon
AU - Ko, Yohan
AU - Lee, Jongwon
AU - Kim, Yongjoo
AU - So, Hwisoo
AU - Lee, Kyoungwoo
AU - Paek, Yunheung
PY - 2013/9/9
Y1 - 2013/9/9
N2 - Coarse-Grained Reconfigurable Architectures or CGRAs are drawing significant attention since they promise both performance with parallelism and flexibility with reconfiguration. Soft errors or transient faults are becoming a serious design concern in embedded systems including CGRAs since soft error rate is increasing exponentially as technology scaling. A recently proposed software-based technique with TMR (Triple Modular Redundancy) implemented on CGRAs incurs extreme performance overhead mainly due to expensive voting mechanisms for outputs from triplication of every operation. In this paper, we propose selective validation mechanisms for efficient modular redundancy techniques in the datapaths on CGRAs. Our techniques selectively validate results at synchronous operations rather than every operation in order to reduce the expensive performance overhead from the validation mechanism. Our experimental results demonstrate that our selective validation based TMR technique can improve the performance by 38.3% on average over benchmarks as compared to the recently proposed software-based TMR technique with the full validation.
AB - Coarse-Grained Reconfigurable Architectures or CGRAs are drawing significant attention since they promise both performance with parallelism and flexibility with reconfiguration. Soft errors or transient faults are becoming a serious design concern in embedded systems including CGRAs since soft error rate is increasing exponentially as technology scaling. A recently proposed software-based technique with TMR (Triple Modular Redundancy) implemented on CGRAs incurs extreme performance overhead mainly due to expensive voting mechanisms for outputs from triplication of every operation. In this paper, we propose selective validation mechanisms for efficient modular redundancy techniques in the datapaths on CGRAs. Our techniques selectively validate results at synchronous operations rather than every operation in order to reduce the expensive performance overhead from the validation mechanism. Our experimental results demonstrate that our selective validation based TMR technique can improve the performance by 38.3% on average over benchmarks as compared to the recently proposed software-based TMR technique with the full validation.
UR - http://www.scopus.com/inward/record.url?scp=84883380388&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84883380388&partnerID=8YFLogxK
U2 - 10.1109/ASAP.2013.6567558
DO - 10.1109/ASAP.2013.6567558
M3 - Conference contribution
AN - SCOPUS:84883380388
SN - 9781479904921
T3 - Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors
SP - 95
EP - 98
BT - ASAP 2013 - Proceedings of the 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors
ER -