Self-aligned III-V MOSFETs heterointegrated on a 200 mm Si substrate using an industry standard process flow

R. J.W. Hill, C. Park, J. Barnett, J. Price, J. Huang, N. Goel, W. Y. Loh, J. Oh, C. E. Smith, P. Kirsch, P. Majhi, R. Jammy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

Abstract

We present the first demonstration of a III-V MOSFET heterointegrated on a large diameter Si substrate and fabricated with a VLSI compatible process flow using a high-k/metal gate, self-aligned implants and refractory Au free ohmic metal. Additionally, TXRF data shows that with the correct protocols III-V and Si devices can be processed side by side in the same Si fabrication line The Lg = 500 nm device has a excellent drive current of ∼450 μA/μm and intrinsic transconductance of ∼1000 μS/μm indicating that III-V VLSI integration is a serious contender for insertion at or beyond the 11 nm technology generation.

Original languageEnglish
Title of host publication2010 IEEE International Electron Devices Meeting, IEDM 2010
Pages6.2.1-6.2.4
DOIs
Publication statusPublished - 2010
Event2010 IEEE International Electron Devices Meeting, IEDM 2010 - San Francisco, CA, United States
Duration: 2010 Dec 62010 Dec 8

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)0163-1918

Other

Other2010 IEEE International Electron Devices Meeting, IEDM 2010
CountryUnited States
CitySan Francisco, CA
Period10/12/610/12/8

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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