Self-aligned III-V MOSFETs heterointegrated on a 200 mm Si substrate using an industry standard process flow

R. J.W. Hill; C. Park; J. Barnett; J. Price; J. Huang; N. Goel; W. Y. Loh; J. Oh; C. E. Smith; P. Kirsch; P. Majhi; R. Jammy

doi:10.1109/IEDM.2010.5703307

Self-aligned III-V MOSFETs heterointegrated on a 200 mm Si substrate using an industry standard process flow

R. J.W. Hill, C. Park, J. Barnett, J. Price, J. Huang, N. Goel, W. Y. Loh, J. Oh, C. E. Smith, P. Kirsch, P. Majhi, R. Jammy

School of Integrated Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

13 Citations (Scopus)

Abstract

We present the first demonstration of a III-V MOSFET heterointegrated on a large diameter Si substrate and fabricated with a VLSI compatible process flow using a high-k/metal gate, self-aligned implants and refractory Au free ohmic metal. Additionally, TXRF data shows that with the correct protocols III-V and Si devices can be processed side by side in the same Si fabrication line The L_g = 500 nm device has a excellent drive current of ∼450 μA/μm and intrinsic transconductance of ∼1000 μS/μm indicating that III-V VLSI integration is a serious contender for insertion at or beyond the 11 nm technology generation.

Original language	English
Title of host publication	2010 IEEE International Electron Devices Meeting, IEDM 2010
Pages	6.2.1-6.2.4
DOIs	https://doi.org/10.1109/IEDM.2010.5703307
Publication status	Published - 2010
Event	2010 IEEE International Electron Devices Meeting, IEDM 2010 - San Francisco, CA, United States Duration: 2010 Dec 6 → 2010 Dec 8

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)	0163-1918

Other

Other	2010 IEEE International Electron Devices Meeting, IEDM 2010
Country/Territory	United States
City	San Francisco, CA
Period	10/12/6 → 10/12/8

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

Access to Document

10.1109/IEDM.2010.5703307

Cite this

Hill, R. J. W., Park, C., Barnett, J., Price, J., Huang, J., Goel, N., Loh, W. Y., Oh, J., Smith, C. E., Kirsch, P., Majhi, P., & Jammy, R. (2010). Self-aligned III-V MOSFETs heterointegrated on a 200 mm Si substrate using an industry standard process flow. In 2010 IEEE International Electron Devices Meeting, IEDM 2010 (pp. 6.2.1-6.2.4). [5703307] (Technical Digest - International Electron Devices Meeting, IEDM). https://doi.org/10.1109/IEDM.2010.5703307

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title = "Self-aligned III-V MOSFETs heterointegrated on a 200 mm Si substrate using an industry standard process flow",

abstract = "We present the first demonstration of a III-V MOSFET heterointegrated on a large diameter Si substrate and fabricated with a VLSI compatible process flow using a high-k/metal gate, self-aligned implants and refractory Au free ohmic metal. Additionally, TXRF data shows that with the correct protocols III-V and Si devices can be processed side by side in the same Si fabrication line The Lg = 500 nm device has a excellent drive current of ∼450 μA/μm and intrinsic transconductance of ∼1000 μS/μm indicating that III-V VLSI integration is a serious contender for insertion at or beyond the 11 nm technology generation.",

author = "Hill, {R. J.W.} and C. Park and J. Barnett and J. Price and J. Huang and N. Goel and Loh, {W. Y.} and J. Oh and Smith, {C. E.} and P. Kirsch and P. Majhi and R. Jammy",

year = "2010",

doi = "10.1109/IEDM.2010.5703307",

language = "English",

isbn = "9781424474196",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

pages = "6.2.1--6.2.4",

booktitle = "2010 IEEE International Electron Devices Meeting, IEDM 2010",

note = "2010 IEEE International Electron Devices Meeting, IEDM 2010 ; Conference date: 06-12-2010 Through 08-12-2010",

}

Hill, RJW, Park, C, Barnett, J, Price, J, Huang, J, Goel, N, Loh, WY, Oh, J, Smith, CE, Kirsch, P, Majhi, P & Jammy, R 2010, Self-aligned III-V MOSFETs heterointegrated on a 200 mm Si substrate using an industry standard process flow. in 2010 IEEE International Electron Devices Meeting, IEDM 2010., 5703307, Technical Digest - International Electron Devices Meeting, IEDM, pp. 6.2.1-6.2.4, 2010 IEEE International Electron Devices Meeting, IEDM 2010, San Francisco, CA, United States, 10/12/6. https://doi.org/10.1109/IEDM.2010.5703307

Self-aligned III-V MOSFETs heterointegrated on a 200 mm Si substrate using an industry standard process flow. / Hill, R. J.W.; Park, C.; Barnett, J. et al.

2010 IEEE International Electron Devices Meeting, IEDM 2010. 2010. p. 6.2.1-6.2.4 5703307 (Technical Digest - International Electron Devices Meeting, IEDM).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Goel, N.

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AB - We present the first demonstration of a III-V MOSFET heterointegrated on a large diameter Si substrate and fabricated with a VLSI compatible process flow using a high-k/metal gate, self-aligned implants and refractory Au free ohmic metal. Additionally, TXRF data shows that with the correct protocols III-V and Si devices can be processed side by side in the same Si fabrication line The Lg = 500 nm device has a excellent drive current of ∼450 μA/μm and intrinsic transconductance of ∼1000 μS/μm indicating that III-V VLSI integration is a serious contender for insertion at or beyond the 11 nm technology generation.

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Self-aligned III-V MOSFETs heterointegrated on a 200 mm Si substrate using an industry standard process flow

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