Self-assembled nanodielectrics and silicon nanomembranes for low voltage, flexible transistors, and logic gates on plastic substrates

Hoon Sik Kim; Sang Min Won; Young Geun Ha; Jong Hyun Ahn; Antonio Facchetti; Tobin J. Marks; John A. Rogers

doi:10.1063/1.3256223

Self-assembled nanodielectrics and silicon nanomembranes for low voltage, flexible transistors, and logic gates on plastic substrates

Hoon Sik Kim, Sang Min Won, Young Geun Ha, Jong Hyun Ahn, Antonio Facchetti, Tobin J. Marks, John A. Rogers

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

30 Citations (Scopus)

Abstract

This letter reports the fabrication and electrical characterization of mechanically flexible and low operating voltage transistors and logic gates (NOT, NAND, and NOR gates) using printed silicon nanomembranes and self-assembled nanodielectrics on thin plastic substrates. The transistors exhibit effective linear mobilities of ∼680 cm² /V s, on/off ratios > 10⁷, gate leakage current densities <2.8× 10-7 A/ cm², and subthreshold slopes ∼120 mV/decade. The inverters show voltage gains as high as 4.8. Simple digital logic gates (NAND and NOR gates) demonstrate the possible application of this materials combination in digital integrated circuits.

Original language	English
Article number	183504
Journal	Applied Physics Letters
Volume	95
Issue number	18
DOIs	https://doi.org/10.1063/1.3256223
Publication status	Published - 2009

Bibliographical note

Funding Information:
We thank T. Banks for help in processing by use of facilities at the Frederick Seitz Materials Research Laboratory. The silicon and device components of the work were supported by a MURI award. The work on SANDs was supported at Northwestern University by ONR (Grant No. N00014-05-1-0766) and AFOSR (Grant No. FA9550-08-1-0331). Characterization facilities were provided by the Northwestern University MRSEC (NSF under Grant No. DMR-0520513).

All Science Journal Classification (ASJC) codes

Physics and Astronomy (miscellaneous)

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title = "Self-assembled nanodielectrics and silicon nanomembranes for low voltage, flexible transistors, and logic gates on plastic substrates",

abstract = "This letter reports the fabrication and electrical characterization of mechanically flexible and low operating voltage transistors and logic gates (NOT, NAND, and NOR gates) using printed silicon nanomembranes and self-assembled nanodielectrics on thin plastic substrates. The transistors exhibit effective linear mobilities of ∼680 cm2 /V s, on/off ratios > 107, gate leakage current densities <2.8× 10-7 A/ cm2, and subthreshold slopes ∼120 mV/decade. The inverters show voltage gains as high as 4.8. Simple digital logic gates (NAND and NOR gates) demonstrate the possible application of this materials combination in digital integrated circuits.",

author = "Kim, {Hoon Sik} and Won, {Sang Min} and Ha, {Young Geun} and Ahn, {Jong Hyun} and Antonio Facchetti and Marks, {Tobin J.} and Rogers, {John A.}",

note = "Funding Information: We thank T. Banks for help in processing by use of facilities at the Frederick Seitz Materials Research Laboratory. The silicon and device components of the work were supported by a MURI award. The work on SANDs was supported at Northwestern University by ONR (Grant No. N00014-05-1-0766) and AFOSR (Grant No. FA9550-08-1-0331). Characterization facilities were provided by the Northwestern University MRSEC (NSF under Grant No. DMR-0520513).",

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AU - Kim, Hoon Sik

AU - Won, Sang Min

AU - Ha, Young Geun

AU - Ahn, Jong Hyun

AU - Facchetti, Antonio

AU - Marks, Tobin J.

AU - Rogers, John A.

N1 - Funding Information: We thank T. Banks for help in processing by use of facilities at the Frederick Seitz Materials Research Laboratory. The silicon and device components of the work were supported by a MURI award. The work on SANDs was supported at Northwestern University by ONR (Grant No. N00014-05-1-0766) and AFOSR (Grant No. FA9550-08-1-0331). Characterization facilities were provided by the Northwestern University MRSEC (NSF under Grant No. DMR-0520513).

PY - 2009

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N2 - This letter reports the fabrication and electrical characterization of mechanically flexible and low operating voltage transistors and logic gates (NOT, NAND, and NOR gates) using printed silicon nanomembranes and self-assembled nanodielectrics on thin plastic substrates. The transistors exhibit effective linear mobilities of ∼680 cm2 /V s, on/off ratios > 107, gate leakage current densities <2.8× 10-7 A/ cm2, and subthreshold slopes ∼120 mV/decade. The inverters show voltage gains as high as 4.8. Simple digital logic gates (NAND and NOR gates) demonstrate the possible application of this materials combination in digital integrated circuits.

AB - This letter reports the fabrication and electrical characterization of mechanically flexible and low operating voltage transistors and logic gates (NOT, NAND, and NOR gates) using printed silicon nanomembranes and self-assembled nanodielectrics on thin plastic substrates. The transistors exhibit effective linear mobilities of ∼680 cm2 /V s, on/off ratios > 107, gate leakage current densities <2.8× 10-7 A/ cm2, and subthreshold slopes ∼120 mV/decade. The inverters show voltage gains as high as 4.8. Simple digital logic gates (NAND and NOR gates) demonstrate the possible application of this materials combination in digital integrated circuits.

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Self-assembled nanodielectrics and silicon nanomembranes for low voltage, flexible transistors, and logic gates on plastic substrates

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All Science Journal Classification (ASJC) codes

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