Self-assembled nanodielectrics and silicon nanomembranes for low voltage, flexible transistors, and logic gates on plastic substrates

Hoon Sik Kim, Sang Min Won, Young Geun Ha, Jong-Hyun Ahn, Antonio Facchetti, Tobin J. Marks, John A. Rogers

Research output: Contribution to journal › Article

24 Citations (Scopus)

Abstract

This letter reports the fabrication and electrical characterization of mechanically flexible and low operating voltage transistors and logic gates (NOT, NAND, and NOR gates) using printed silicon nanomembranes and self-assembled nanodielectrics on thin plastic substrates. The transistors exhibit effective linear mobilities of ∼680 cm2 /V s, on/off ratios > 107, gate leakage current densities <2.8× 10-7 A/ cm2, and subthreshold slopes ∼120 mV/decade. The inverters show voltage gains as high as 4.8. Simple digital logic gates (NAND and NOR gates) demonstrate the possible application of this materials combination in digital integrated circuits.

Original languageEnglish
Article number183504
JournalApplied Physics Letters
Volume95
Issue number18
DOIs
Publication statusPublished - 2009 Nov 16

Fingerprint

low voltage
logic
transistors
plastics
silicon
inverters
electric potential
integrated circuits
leakage
current density
slopes
fabrication

All Science Journal Classification (ASJC) codes

  • Physics and Astronomy (miscellaneous)

Cite this

Kim, Hoon Sik ; Won, Sang Min ; Ha, Young Geun ; Ahn, Jong-Hyun ; Facchetti, Antonio ; Marks, Tobin J. ; Rogers, John A. / Self-assembled nanodielectrics and silicon nanomembranes for low voltage, flexible transistors, and logic gates on plastic substrates. In: Applied Physics Letters. 2009 ; Vol. 95, No. 18.
@article{37bc67724b3148fc855521787e303be8,
title = "Self-assembled nanodielectrics and silicon nanomembranes for low voltage, flexible transistors, and logic gates on plastic substrates",
abstract = "This letter reports the fabrication and electrical characterization of mechanically flexible and low operating voltage transistors and logic gates (NOT, NAND, and NOR gates) using printed silicon nanomembranes and self-assembled nanodielectrics on thin plastic substrates. The transistors exhibit effective linear mobilities of ∼680 cm2 /V s, on/off ratios > 107, gate leakage current densities <2.8× 10-7 A/ cm2, and subthreshold slopes ∼120 mV/decade. The inverters show voltage gains as high as 4.8. Simple digital logic gates (NAND and NOR gates) demonstrate the possible application of this materials combination in digital integrated circuits.",
author = "Kim, {Hoon Sik} and Won, {Sang Min} and Ha, {Young Geun} and Jong-Hyun Ahn and Antonio Facchetti and Marks, {Tobin J.} and Rogers, {John A.}",
year = "2009",
month = "11",
day = "16",
doi = "10.1063/1.3256223",
language = "English",
volume = "95",
journal = "Applied Physics Letters",
issn = "0003-6951",
publisher = "American Institute of Physics Publising LLC",
number = "18",

}

Kim, HS, Won, SM, Ha, YG, Ahn, J-H, Facchetti, A, Marks, TJ & Rogers, JA 2009, 'Self-assembled nanodielectrics and silicon nanomembranes for low voltage, flexible transistors, and logic gates on plastic substrates', Applied Physics Letters, vol. 95, no. 18, 183504. https://doi.org/10.1063/1.3256223

Self-assembled nanodielectrics and silicon nanomembranes for low voltage, flexible transistors, and logic gates on plastic substrates. / Kim, Hoon Sik; Won, Sang Min; Ha, Young Geun; Ahn, Jong-Hyun; Facchetti, Antonio; Marks, Tobin J.; Rogers, John A.

In: Applied Physics Letters, Vol. 95, No. 18, 183504, 16.11.2009.

Research output: Contribution to journal › Article

TY - JOUR

T1 - Self-assembled nanodielectrics and silicon nanomembranes for low voltage, flexible transistors, and logic gates on plastic substrates

AU - Kim, Hoon Sik

AU - Won, Sang Min

AU - Ha, Young Geun

AU - Ahn, Jong-Hyun

AU - Facchetti, Antonio

AU - Marks, Tobin J.

AU - Rogers, John A.

PY - 2009/11/16

Y1 - 2009/11/16

N2 - This letter reports the fabrication and electrical characterization of mechanically flexible and low operating voltage transistors and logic gates (NOT, NAND, and NOR gates) using printed silicon nanomembranes and self-assembled nanodielectrics on thin plastic substrates. The transistors exhibit effective linear mobilities of ∼680 cm2 /V s, on/off ratios > 107, gate leakage current densities <2.8× 10-7 A/ cm2, and subthreshold slopes ∼120 mV/decade. The inverters show voltage gains as high as 4.8. Simple digital logic gates (NAND and NOR gates) demonstrate the possible application of this materials combination in digital integrated circuits.

AB - This letter reports the fabrication and electrical characterization of mechanically flexible and low operating voltage transistors and logic gates (NOT, NAND, and NOR gates) using printed silicon nanomembranes and self-assembled nanodielectrics on thin plastic substrates. The transistors exhibit effective linear mobilities of ∼680 cm2 /V s, on/off ratios > 107, gate leakage current densities <2.8× 10-7 A/ cm2, and subthreshold slopes ∼120 mV/decade. The inverters show voltage gains as high as 4.8. Simple digital logic gates (NAND and NOR gates) demonstrate the possible application of this materials combination in digital integrated circuits.

UR - http://www.scopus.com/inward/record.url?scp=71049115204&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=71049115204&partnerID=8YFLogxK

U2 - 10.1063/1.3256223

DO - 10.1063/1.3256223

M3 - Article

VL - 95

JO - Applied Physics Letters

JF - Applied Physics Letters

SN - 0003-6951

IS - 18

M1 - 183504

ER -

Kim HS, Won SM, Ha YG, Ahn J-H, Facchetti A, Marks TJ et al. Self-assembled nanodielectrics and silicon nanomembranes for low voltage, flexible transistors, and logic gates on plastic substrates. Applied Physics Letters. 2009 Nov 16;95(18). 183504. https://doi.org/10.1063/1.3256223

Access to Document