This letter reports the fabrication and electrical characterization of mechanically flexible and low operating voltage transistors and logic gates (NOT, NAND, and NOR gates) using printed silicon nanomembranes and self-assembled nanodielectrics on thin plastic substrates. The transistors exhibit effective linear mobilities of ∼680 cm2 /V s, on/off ratios > 107, gate leakage current densities <2.8× 10-7 A/ cm2, and subthreshold slopes ∼120 mV/decade. The inverters show voltage gains as high as 4.8. Simple digital logic gates (NAND and NOR gates) demonstrate the possible application of this materials combination in digital integrated circuits.
Bibliographical noteFunding Information:
We thank T. Banks for help in processing by use of facilities at the Frederick Seitz Materials Research Laboratory. The silicon and device components of the work were supported by a MURI award. The work on SANDs was supported at Northwestern University by ONR (Grant No. N00014-05-1-0766) and AFOSR (Grant No. FA9550-08-1-0331). Characterization facilities were provided by the Northwestern University MRSEC (NSF under Grant No. DMR-0520513).
All Science Journal Classification (ASJC) codes
- Physics and Astronomy (miscellaneous)