Abstract
This letter reports the fabrication and electrical characterization of mechanically flexible and low operating voltage transistors and logic gates (NOT, NAND, and NOR gates) using printed silicon nanomembranes and self-assembled nanodielectrics on thin plastic substrates. The transistors exhibit effective linear mobilities of ∼680 cm2 /V s, on/off ratios > 107, gate leakage current densities <2.8× 10-7 A/ cm2, and subthreshold slopes ∼120 mV/decade. The inverters show voltage gains as high as 4.8. Simple digital logic gates (NAND and NOR gates) demonstrate the possible application of this materials combination in digital integrated circuits.
| Original language | English |
|---|---|
| Article number | 183504 |
| Journal | Applied Physics Letters |
| Volume | 95 |
| Issue number | 18 |
| DOIs | |
| Publication status | Published - 2009 Nov 16 |
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All Science Journal Classification (ASJC) codes
- Physics and Astronomy (miscellaneous)
Cite this
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Self-assembled nanodielectrics and silicon nanomembranes for low voltage, flexible transistors, and logic gates on plastic substrates. / Kim, Hoon Sik; Won, Sang Min; Ha, Young Geun; Ahn, Jong Hyun; Facchetti, Antonio; Marks, Tobin J.; Rogers, John A.
In: Applied Physics Letters, Vol. 95, No. 18, 183504, 16.11.2009.Research output: Contribution to journal › Article
TY - JOUR
T1 - Self-assembled nanodielectrics and silicon nanomembranes for low voltage, flexible transistors, and logic gates on plastic substrates
AU - Kim, Hoon Sik
AU - Won, Sang Min
AU - Ha, Young Geun
AU - Ahn, Jong Hyun
AU - Facchetti, Antonio
AU - Marks, Tobin J.
AU - Rogers, John A.
PY - 2009/11/16
Y1 - 2009/11/16
N2 - This letter reports the fabrication and electrical characterization of mechanically flexible and low operating voltage transistors and logic gates (NOT, NAND, and NOR gates) using printed silicon nanomembranes and self-assembled nanodielectrics on thin plastic substrates. The transistors exhibit effective linear mobilities of ∼680 cm2 /V s, on/off ratios > 107, gate leakage current densities <2.8× 10-7 A/ cm2, and subthreshold slopes ∼120 mV/decade. The inverters show voltage gains as high as 4.8. Simple digital logic gates (NAND and NOR gates) demonstrate the possible application of this materials combination in digital integrated circuits.
AB - This letter reports the fabrication and electrical characterization of mechanically flexible and low operating voltage transistors and logic gates (NOT, NAND, and NOR gates) using printed silicon nanomembranes and self-assembled nanodielectrics on thin plastic substrates. The transistors exhibit effective linear mobilities of ∼680 cm2 /V s, on/off ratios > 107, gate leakage current densities <2.8× 10-7 A/ cm2, and subthreshold slopes ∼120 mV/decade. The inverters show voltage gains as high as 4.8. Simple digital logic gates (NAND and NOR gates) demonstrate the possible application of this materials combination in digital integrated circuits.
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UR - http://www.scopus.com/inward/citedby.url?scp=71049115204&partnerID=8YFLogxK
U2 - 10.1063/1.3256223
DO - 10.1063/1.3256223
M3 - Article
AN - SCOPUS:71049115204
VL - 95
JO - Applied Physics Letters
JF - Applied Physics Letters
SN - 0003-6951
IS - 18
M1 - 183504
ER -